Commit 3e0ba410 authored by Ralf Baechle's avatar Ralf Baechle
Browse files

[MIPS] IP27: Remove #if 0'ed code.


Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent 8f2f360d
......@@ -69,13 +69,6 @@ typedef s32 klconf_off_t;
/*
* Some IMPORTANT OFFSETS. These are the offsets on all NODES.
*/
#if 0
#define RAMBASE 0
#define ARCSSPB_OFF 0x1000 /* shift it to sys/arcs/spb.h */
#define OFF_HWGRAPH 0
#endif
#define MAX_MODULE_ID 255
#define SIZE_PAD 4096 /* 4k padding for structures */
/*
......@@ -164,10 +157,6 @@ typedef struct kl_config_hdr {
#define KL_CONFIG_HDR(_nasid) ((kl_config_hdr_t *)(KLCONFIG_ADDR(_nasid)))
#if 0
#define KL_CONFIG_MALLOC_HDR(_nasid) \
(KL_CONFIG_HDR(_nasid)->ch_malloc_hdr)
#endif
#define KL_CONFIG_INFO_OFFSET(_nasid) \
(KL_CONFIG_HDR(_nasid)->ch_board_info)
#define KL_CONFIG_INFO_SET_OFFSET(_nasid, _off) \
......@@ -601,18 +590,6 @@ typedef struct klport_s {
klconf_off_t port_offset;
} klport_t;
#if 0
/*
* This is very similar to the klport_s but instead of having a componant
* offset it has a board offset.
*/
typedef struct klxbow_port_s {
nasid_t port_nasid;
unsigned char port_flag;
klconf_off_t board_offset;
} klxbow_port_t;
#endif
typedef struct klcpu_s { /* CPU */
klinfo_t cpu_info;
unsigned short cpu_prid; /* Processor PRID value */
......
......@@ -486,22 +486,6 @@ typedef union h1_icrba_u {
#define ICRBN_A_CERR_SHFT 54
#define ICRBN_A_ERR_MASK 0x3ff
#if 0 /* Disabled, this causes namespace polution and break allmodconfig */
/*
* Easy access macros.
*/
#define a_error icrba_fields_s.error
#define a_ecode icrba_fields_s.ecode
#define a_lnetuce icrba_fields_s.lnetuce
#define a_mark icrba_fields_s.mark
#define a_xerr icrba_fields_s.xerr
#define a_sidn icrba_fields_s.sidn
#define a_tnum icrba_fields_s.tnum
#define a_addr icrba_fields_s.addr
#define a_valid icrba_fields_s.valid
#define a_iow icrba_fields_s.iow
#endif
#endif /* !__ASSEMBLY__ */
#define IIO_ICRB_ADDR_SHFT 2 /* Shift to get proper address */
......
......@@ -398,24 +398,6 @@ typedef u64 rtc_time_t;
/* PI_RT_FILTER_CTRL mask and shift definitions */
#if 0
/*
* XXX - This register's definition has changed, but it's only implemented
* in Hub 2.
*/
#define PRFC_DROP_COUNT_SHFT 27
#define PRFC_DROP_COUNT_MASK (UINT64_CAST 0x3ff << 27)
#define PRFC_DROP_CTR_SHFT 18
#define PRFC_DROP_CTR_MASK (UINT64_CAST 0x1ff << 18)
#define PRFC_MASK_ENABLE_SHFT 10
#define PRFC_MASK_ENABLE_MASK (UINT64_CAST 0x7f << 10)
#define PRFC_MASK_CTR_SHFT 2
#define PRFC_MASK_CTR_MASK (UINT64_CAST 0xff << 2)
#define PRFC_OFFSET_SHFT 0
#define PRFC_OFFSET_MASK (UINT64_CAST 3)
#endif /* 0 */
/*
* Bits for NACK_CNT_A/B and NACK_CMP
*/
......
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