• Peter Maydell's avatar
    target-arm: Make *IS TLB maintenance ops affect all CPUs · fa439fc5
    Peter Maydell authored
    The ARM architecture defines that the "IS" variants of TLB
    maintenance operations must affect all TLBs in the Inner Shareable
    domain, which for us means all CPUs. We were incorrectly implementing
    these to only affect the current CPU, which meant that SMP TCG
    operation was unstable.
    Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
    Message-id: 1410274883-9578-3-git-send-email-peter.maydell@linaro.org
    Cc: qemu-stable@nongnu.org
    fa439fc5
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