• Paolo Bonzini's avatar
    apic: fix incorrect handling of ExtINT interrupts wrt processor priority · 5224c88d
    Paolo Bonzini authored
    This fixes another failure with ExtINT, demonstrated by QNX.  The failure
    mode is as follows:
    - IPI sent to cpu 0 (bit set in APIC irr)
    - IPI accepted by cpu 0 (bit cleared in irr, set in isr)
    - IPI sent to cpu 0 (bit set in both irr and isr)
    - PIC interrupt sent to cpu 0
    
    The PIC interrupt causes CPU_INTERRUPT_HARD to be set, but
    apic_irq_pending observes that the highest pending APIC interrupt priority
    (the IPI) is the same as the processor priority (since the IPI is still
    being handled), so apic_get_interrupt returns a spurious interrupt rather
    than the pending PIC interrupt. The result is an endless sequence of
    spurious interrupts, since nothing will clear CPU_INTERRUPT_HARD.
    
    Instead, ExtINT interrupts should have ignored the processor priority.
    Calling apic_check_pic early in apic_get_interrupt ensures that
    apic_deliver_pic_intr is called instead of delivering the spurious
    interrupt.  apic_deliver_pic_intr then clears CPU_INTERRUPT_HARD if needed.
    Reported-by: default avatarRichard Bilson <rbilson@qnx.com>
    Tested-by: default avatarRichard Bilson <rbilson@qnx.com>
    Signed-off-by: default avatarPaolo Bonzini <pbonzini@redhat.com>
    5224c88d
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