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Maciej W. Rozycki authored
Set the CP0.Config3.DSP2P bit for the 74kf processor and both that bit and the CP0.Config3.DSP bit for the artificial mips32r5-generic and mips64dspr2 processors. They have the DSPr2 ASE enabled in `insn_flags' and CPUs that implement that ASE need to have both CP0.Config3.DSP and CP0.Config3.DSP2P set or software won't detect its presence. Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com> Reviewed-by: Leon Alrae <leon.alrae@imgtec.com> [leon.alrae@imgtec.com: remove DSP flags from mips32r5-generic] Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
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