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Isaku Yamahata authored
Trigger secondary bus reset when secondary bus reset bit value changes from 0 to 1. Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
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