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  • Nathan Froyd's avatar
    MIPS: Correct FCR0 initialization · f1cb0951
    Nathan Froyd authored
    
    
     This change addresses a problem where QEMU incorrectly traps on
    floating-point MADD group instructions with SIGILL, at least while
    emulating MIPS32r2 processors.  These instructions use the COP1X major
    opcode and include ones like:
    
    	madd.d	$f2,$f4,$f2,$f6
    
     Here's Nathan's original analysis of the problem:
    
    "QEMU essentially does:
    
      d = find_cpu (cpu_string)	// get CPU definition
      fpu_init (env, d)		// initialize fpu state (init FCR0, basically)
      cpu_reset (env)
    
    ...and the cpu_reset call clears all interesting state that fpu_init
    setup, then proceeds to reinitialize all the CP0 registers...but not
    FCR0."
    
     I have verified this change with system emulation running the GDB test
    suite for the mips-sde-elf target (o32, big endian, 24Kf CPU emulated),
    there were 55 progressions and no regressions.
    
    Signed-off-by: default avatarMaciej W. Rozycki <macro@codesourcery.com>
    Reviewed-by: default avatarRichard Henderson <rth@twiddle.net>
    Signed-off-by: default avatarBlue Swirl <blauwirbel@gmail.com>
    f1cb0951