• Chao Xie's avatar
    clk: mmp: add clock type mix · ee81f4ee
    Chao Xie authored
    The clock type mix is a kind of clock combines "div" and "mux".
    This kind of clock can not allow to change div first then
    mux or change mux first or div.
    The reason is
    1. Some clock has frequency change bit. Each time want to change
       the frequency, there are some operations based on this bit, and
       these operations are time-cost.
       Seperating div and mux change will make the process longer, and
       waste more time.
    2. Seperting the div and mux may generate middle clock that the
       peripharals do not support. It may make the peripharals hang.
    
    There are three kinds of this type of clock in all SOCes.
    1. The clock has bit to trigger the frequency change.
    2. Same as #1, but the operations for the bit is different
    3. Do not have frequency change bit.
    
    So this type of clock has implemented the callbacks
    ->determine_rate
    ->set_rate_and_parent
    These callbacks can help to change the div and mux together.
    Signed-off-by: default avatarChao Xie <chao.xie@marvell.com>
    Acked-by: default avatarHaojian Zhuang <haojian.zhuang@gmail.com>
    Signed-off-by: default avatarMichael Turquette <mturquette@linaro.org>
    ee81f4ee
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