• Vladimir Zapolskiy's avatar
    irqchip: Add LPC32xx interrupt controller driver · 8cb17b5e
    Vladimir Zapolskiy authored
    The change adds improved support of NXP LPC32xx MIC, SIC1 and SIC2
    interrupt controllers.
    
    This is a list of new features in comparison to the legacy driver:
    * irq types are taken from device tree settings, no more need to
      hardcode them,
    * old driver is based on irq_domain_add_legacy, which causes problems
      with handling MIC hardware interrupt 0 produced by SIC1,
    * there is one driver for MIC, SIC1 and SIC2, no more need to handle
      them separately, e.g. have two separate handlers for SIC1 and SIC2,
    * the driver does not have any dependencies on hardcoded register
      offsets,
    * the driver is much simpler for maintenance,
    * SPARSE_IRQS option is supported.
    
    Legacy LPC32xx interrupt controller driver was broken since commit
    76ba59f8 ("genirq: Add irq_domain-aware core IRQ handler"), which
    requires a private interrupt handler, otherwise any SIC1 generated
    interrupt (mapped to MIC hwirq 0) breaks the kernel with the message
    "unexpected IRQ trap at vector 00".
    
    The change disables compilation of a legacy driver found at
    arch/arm/mach-lpc32xx/irq.c, the file will be removed in a separate
    commit.
    
    Fixes: 76ba59f8 ("genirq: Add irq_domain-aware core IRQ handler")
    Tested-by: default avatarSylvain Lemieux <slemieux.tyco@gmail.com>
    Signed-off-by: default avatarVladimir Zapolskiy <vz@mleia.com>
    Signed-off-by: default avatarMarc Zyngier <marc.zyngier@arm.com>
    8cb17b5e