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11 authors
  1. Mar 31, 2011
  3. Mar 22, 2011
  5. Mar 16, 2011
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    • Anatolij Gustschin's avatar
      USB: add USB EHCI support for MPC5121 SoC · 230f7ede
      Anatolij Gustschin authored 
      
Extends FSL EHCI platform driver glue layer to support
MPC5121 USB controllers. MPC5121 Rev 2.0 silicon EHCI
registers are in big endian format. The appropriate flags
are set using the information in the platform data structure.
MPC83xx system interface registers are not available on
MPC512x, so the access to these registers is isolated in
MPC512x case. Furthermore the USB controller clocks
must be enabled before 512x register accesses which is
done by providing platform specific init callback.

The MPC512x internal USB PHY doesn't provide supply voltage.
For boards using different power switches allow specifying
DRVVBUS and PWR_FAULT signal polarity of the MPC5121 internal
PHY using "fsl,invert-drvvbus" and "fsl,invert-pwr-fault"
properties in the device tree USB nodes. Adds documentation
for this new device tree bindings.

Signed-off-by: default avatarAnatolij Gustschin <agust@denx.de>
Cc: Grant Likely <grant.likely@secretlab.ca>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@suse.de>
      230f7ede
  21. Oct 12, 2010
  23. Aug 20, 2010
  25. Aug 16, 2010
  27. Aug 11, 2010
  29. Aug 04, 2010
    • Justin P. Mattock's avatar
      Documentation: update broken web addresses. · 0ea6e611
      Justin P. Mattock authored 
      
Below you will find an updated version from the original series bunching all patches into one big patch
updating broken web addresses that are located in Documentation/*
Some of the addresses date as far far back as 1995 etc... so searching became a bit difficult,
the best way to deal with these is to use web.archive.org to locate these addresses that are outdated.
Now there are also some addresses pointing to .spec files some are located, but some(after searching
on the companies site)where still no where to be found. In this case I just changed the address
to the company site this way the users can contact the company and they can locate them for the users.

Signed-off-by: default avatarJustin P. Mattock <justinmattock@gmail.com>
Signed-off-by: default avatarThomas Weber <weber@corscience.de>
Signed-off-by: default avatarMike Frysinger <vapier.adi@gmail.com>
Cc: Paulo Marques <pmarques@grupopie.com>
Cc: Randy Dunlap <rdunlap@xenotime.net>
Cc: Michael Neuling <mikey@neuling.org>
Signed-off-by: default avatarJiri Kosina <jkosina@suse.cz>
      0ea6e611
  31. Aug 01, 2010
    • Albrecht Dreß's avatar
      powerpc/5200/i2c: improve i2c bus error recovery · 0c2daaaf
      Albrecht Dreß authored 
      
This patch improves the recovery of the MPC's I2C bus from errors like bus
hangs resulting in timeouts:
1. make the bus timeout configurable, as it depends on the bus clock and
    the attached slave chip(s); default is still 1 second;
2. detect any of the cases indicated by the CF, BB and RXAK MSR flags if a
    timeout occurs, and add a missing (required) MAL reset;
3. use a more reliable method to fixup the bus if a hang has been detected.
    The sequence is sent 9 times which seems to be necessary if a slave
    "misses" more than one clock cycle.  For 400 kHz bus speed, the fixup is
    also ~70us (81us vs. 150us) faster.

Tested on a custom Lite5200b derived board, with a Dallas RTC, AD sensors
and NXP IO expander chips attached to the i2c.

Changes vs. v1:
- use improved bus fixup sequence for all chips (not only the 5200)
- calculate real clock from defaults if no clock is given in the device tree
- better description (I hope) of the changes.

I didn't split the changes in this file into three parts as recommended by
Grant, as they actually belong together (i.e. they address one single
problem, just in three places of one single source file).

Signed-off-by: default avatarAlbrecht Dreß <albrecht.dress@arcor.de>
[grant.likely@secretlab.ca: fixup for ->node to ->dev.of_node transition]
Signed-off-by: default avatarGrant Likely <grant.likely@secretlab.ca>
      0c2daaaf
    • Anatolij Gustschin's avatar
      powerpc/fsl-diu-fb: Support setting display mode using EDID · 8b856f04
      Anatolij Gustschin authored 
      
Adds support for encoding display mode information
in the device tree using verbatim EDID block.

If the EDID entry in the DIU node is present, the
driver will build mode database using EDID data
and allow setting the display modes from this database.
Otherwise display mode will be set using mode
entries from driver's internal database as usual.

This patch also updates device tree bindings.

Signed-off-by: default avatarAnatolij Gustschin <agust@denx.de>
Acked-by: default avatarTimur Tabi <timur@freescale.com>
Signed-off-by: default avatarGrant Likely <grant.likely@secretlab.ca>
      8b856f04
    • Anatolij Gustschin's avatar
      powerpc/5121: doc/dts-bindings: update doc of FSL DIU bindings · a027b333
      Anatolij Gustschin authored 
      
Update compatible and interrupt properties description.
Furthermore an example for the MPC5121 has been added.

Signed-off-by: default avatarAnatolij Gustschin <agust@denx.de>
Acked-by: default avatarTimur Tabi <timur@freescale.com>
Signed-off-by: default avatarGrant Likely <grant.likely@secretlab.ca>
      a027b333
  33. May 17, 2010
  35. May 05, 2010
  37. Apr 22, 2010
  39. Mar 29, 2010
  41. Mar 26, 2010
  43. Mar 07, 2010
  45. Feb 17, 2010
  47. Feb 16, 2010
  49. Feb 02, 2010
    • Ira Snyder's avatar
      fsldma: simplify IRQ probing and handling · d3f620b2
      Ira Snyder authored 
      
The IRQ probing is needlessly complex. All off the 83xx device trees in
arch/powerpc/boot/dts/ specify 5 interrupts per DMA controller: one for the
controller, and one for each channel. These interrupts are all attached to
the same IRQ line.

This causes an interesting situation if two channels interrupt at the same
time. The per-controller handler will handle the first channel, and the
per-channel handler will handle the remaining channels.

Instead of this mess, we fix the bug in the per-controller handler, and
make it handle all channels that generated an interrupt. When a
per-controller handler is specified in the device tree, we prefer to use
the shared handler instead of the per-channel handler.

The 85xx/86xx controllers do not have a per-controller interrupt, and
instead use a per-channel interrupt. This behavior has not been changed.

Signed-off-by: default avatarIra W. Snyder <iws@ovro.caltech.edu>
Signed-off-by: default avatarDan Williams <dan.j.williams@intel.com>
      d3f620b2
  51. Jan 08, 2010
  53. Dec 12, 2009
  55. Dec 11, 2009
  57. Dec 09, 2009
  59. Nov 17, 2009
  61. Nov 13, 2009
  63. Nov 11, 2009
  65. Sep 23, 2009