Commit ce519e23 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/staging-2.6

* git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/staging-2.6: (237 commits)
  Staging: android: binder: fix build errors
  Staging: android: add lowmemorykiller driver
  Staging: android: remove dummy android.c driver
  Staging: android: timed_gpio: Rename android_timed_gpio to timed_gpio
  Staging: android: add timed_gpio driver
  Staging: android: add ram_console driver
  Staging: android: add logging driver
  staging: android: binder: Fix use of euid
  Staging: android: binder: Fix gcc warnings about improper format specifiers for size_t in printk
  Staging: android: add binder driver
  Staging: add android framework
  Staging: epl: fix netdev->priv b0rkage
  Staging: epl: hr timers all run in hard irq context now
  Staging: epl: run Lindent on *.c files
  Staging: epl: run Lindent on *.h files
  Staging: epl: run Lindent on all user/*.h files
  Staging: epl: run Lindent on all kernel/*.h files
  Staging: add epl stack
  Staging: frontier: fix compiler warnings
  Staging: frontier: remove unused alphatrack_sysfs.c file
  ...
parents 40d7ee5d 7a9c67a6
......@@ -1325,6 +1325,8 @@ source "drivers/regulator/Kconfig"
source "drivers/uio/Kconfig"
source "drivers/staging/Kconfig"
endmenu
source "fs/Kconfig"
......
......@@ -681,6 +681,8 @@ source "drivers/usb/Kconfig"
source "drivers/uwb/Kconfig"
source "drivers/staging/Kconfig"
source "arch/cris/Kconfig.debug"
source "security/Kconfig"
......
......@@ -220,6 +220,8 @@ source "drivers/uwb/Kconfig"
endmenu
source "drivers/staging/Kconfig"
source "fs/Kconfig"
source "arch/h8300/Kconfig.debug"
......
......@@ -49,6 +49,8 @@ source "drivers/staging/sxg/Kconfig"
source "drivers/staging/me4000/Kconfig"
source "drivers/staging/meilhaus/Kconfig"
source "drivers/staging/go7007/Kconfig"
source "drivers/staging/usbip/Kconfig"
......@@ -63,5 +65,35 @@ source "drivers/staging/at76_usb/Kconfig"
source "drivers/staging/poch/Kconfig"
source "drivers/staging/agnx/Kconfig"
source "drivers/staging/otus/Kconfig"
source "drivers/staging/rt2860/Kconfig"
source "drivers/staging/rt2870/Kconfig"
source "drivers/staging/benet/Kconfig"
source "drivers/staging/comedi/Kconfig"
source "drivers/staging/asus_oled/Kconfig"
source "drivers/staging/panel/Kconfig"
source "drivers/staging/altpciechdma/Kconfig"
source "drivers/staging/rtl8187se/Kconfig"
source "drivers/staging/rspiusb/Kconfig"
source "drivers/staging/mimio/Kconfig"
source "drivers/staging/frontier/Kconfig"
source "drivers/staging/epl/Kconfig"
source "drivers/staging/android/Kconfig"
endif # !STAGING_EXCLUDE_BUILD
endif # STAGING
......@@ -7,6 +7,7 @@ obj-$(CONFIG_ET131X) += et131x/
obj-$(CONFIG_SLICOSS) += slicoss/
obj-$(CONFIG_SXG) += sxg/
obj-$(CONFIG_ME4000) += me4000/
obj-$(CONFIG_MEILHAUS) += meilhaus/
obj-$(CONFIG_VIDEO_GO7007) += go7007/
obj-$(CONFIG_USB_IP_COMMON) += usbip/
obj-$(CONFIG_W35UND) += winbond/
......@@ -14,3 +15,18 @@ obj-$(CONFIG_PRISM2_USB) += wlan-ng/
obj-$(CONFIG_ECHO) += echo/
obj-$(CONFIG_USB_ATMEL) += at76_usb/
obj-$(CONFIG_POCH) += poch/
obj-$(CONFIG_AGNX) += agnx/
obj-$(CONFIG_OTUS) += otus/
obj-$(CONFIG_RT2860) += rt2860/
obj-$(CONFIG_RT2870) += rt2870/
obj-$(CONFIG_BENET) += benet/
obj-$(CONFIG_COMEDI) += comedi/
obj-$(CONFIG_ASUS_OLED) += asus_oled/
obj-$(CONFIG_PANEL) += panel/
obj-$(CONFIG_ALTERA_PCIE_CHDMA) += altpciechdma/
obj-$(CONFIG_RTL8187SE) += rtl8187se/
obj-$(CONFIG_USB_RSPI) += rspiusb/
obj-$(CONFIG_INPUT_MIMIO) += mimio/
obj-$(CONFIG_TRANZPORT) += frontier/
obj-$(CONFIG_EPL) += epl/
obj-$(CONFIG_ANDROID) += android/
config AGNX
tristate "Wireless Airgo AGNX support"
depends on WLAN_80211 && MAC80211
---help---
This is an experimental driver for Airgo AGNX00 wireless chip.
obj-$(CONFIG_AGNX) += agnx.o
agnx-objs := rf.o \
pci.o \
xmit.o \
table.o \
sta.o \
phy.o
2008 7/18
The RX has can't receive OFDM packet correctly,
Guess it need be do RX calibrate.
before 2008 3/1
1: The RX get too much "CRC failed" pakets, it make the card work very unstable,
2: After running a while, the card will get infinity "RX Frame" and "Error"
interrupt, not know the root reason so far, try to fix it
3: Using two tx queue txd and txm but not only txm.
4: Set the hdr correctly.
5: Try to do recalibrate correvtly
6: To support G mode in future
7: Fix the mac address can't be readed and set correctly in BE machine.
8: Fix include and exclude FCS in promisous mode and manage mode
9: Using sta_notify to notice sta change
10: Turn on frame reception at the end of start
11: Guess the card support HW_MULTICAST_FILTER
12: The tx process should be implment atomic?
13: Using mac80211 function to control the TX&RX LED.
#ifndef AGNX_H_
#define AGNX_H_
#include "xmit.h"
#define PFX KBUILD_MODNAME ": "
static inline u32 agnx_read32(void __iomem *mem_region, u32 offset)
{
return ioread32(mem_region + offset);
}
static inline void agnx_write32(void __iomem *mem_region, u32 offset, u32 val)
{
iowrite32(val, mem_region + offset);
}
/* static const struct ieee80211_rate agnx_rates_80211b[] = { */
/* { .rate = 10, */
/* .val = 0xa, */
/* .flags = IEEE80211_RATE_CCK }, */
/* { .rate = 20, */
/* .val = 0x14, */
/* .hw_value = -0x14, */
/* .flags = IEEE80211_RATE_CCK_2 }, */
/* { .rate = 55, */
/* .val = 0x37, */
/* .val2 = -0x37, */
/* .flags = IEEE80211_RATE_CCK_2 }, */
/* { .rate = 110, */
/* .val = 0x6e, */
/* .val2 = -0x6e, */
/* .flags = IEEE80211_RATE_CCK_2 } */
/* }; */
static const struct ieee80211_rate agnx_rates_80211g[] = {
/* { .bitrate = 10, .hw_value = 1, .flags = IEEE80211_RATE_SHORT_PREAMBLE }, */
/* { .bitrate = 20, .hw_value = 2, .flags = IEEE80211_RATE_SHORT_PREAMBLE }, */
/* { .bitrate = 55, .hw_value = 3, .flags = IEEE80211_RATE_SHORT_PREAMBLE }, */
/* { .bitrate = 110, .hw_value = 4, .flags = IEEE80211_RATE_SHORT_PREAMBLE }, */
{ .bitrate = 10, .hw_value = 1, },
{ .bitrate = 20, .hw_value = 2, },
{ .bitrate = 55, .hw_value = 3, },
{ .bitrate = 110, .hw_value = 4,},
{ .bitrate = 60, .hw_value = 0xB, },
{ .bitrate = 90, .hw_value = 0xF, },
{ .bitrate = 120, .hw_value = 0xA },
{ .bitrate = 180, .hw_value = 0xE, },
// { .bitrate = 240, .hw_value = 0xd, },
{ .bitrate = 360, .hw_value = 0xD, },
{ .bitrate = 480, .hw_value = 0x8, },
{ .bitrate = 540, .hw_value = 0xC, },
};
static const struct ieee80211_channel agnx_channels[] = {
{ .center_freq = 2412, .hw_value = 1, },
{ .center_freq = 2417, .hw_value = 2, },
{ .center_freq = 2422, .hw_value = 3, },
{ .center_freq = 2427, .hw_value = 4, },
{ .center_freq = 2432, .hw_value = 5, },
{ .center_freq = 2437, .hw_value = 6, },
{ .center_freq = 2442, .hw_value = 7, },
{ .center_freq = 2447, .hw_value = 8, },
{ .center_freq = 2452, .hw_value = 9, },
{ .center_freq = 2457, .hw_value = 10, },
{ .center_freq = 2462, .hw_value = 11, },
{ .center_freq = 2467, .hw_value = 12, },
{ .center_freq = 2472, .hw_value = 13, },
{ .center_freq = 2484, .hw_value = 14, },
};
#define NUM_DRIVE_MODES 2
/* Agnx operate mode */
enum {
AGNX_MODE_80211A,
AGNX_MODE_80211A_OOB,
AGNX_MODE_80211A_MIMO,
AGNX_MODE_80211B_SHORT,
AGNX_MODE_80211B_LONG,
AGNX_MODE_80211G,
AGNX_MODE_80211G_OOB,
AGNX_MODE_80211G_MIMO,
};
enum {
AGNX_UNINIT,
AGNX_START,
AGNX_STOP,
};
struct agnx_priv {
struct pci_dev *pdev;
struct ieee80211_hw *hw;
spinlock_t lock;
struct mutex mutex;
unsigned int init_status;
void __iomem *ctl; /* pointer to base ram address */
void __iomem *data; /* pointer to mem region #2 */
struct agnx_ring rx;
struct agnx_ring txm;
struct agnx_ring txd;
/* Need volatile? */
u32 irq_status;
struct delayed_work periodic_work; /* Periodic tasks like recalibrate*/
struct ieee80211_low_level_stats stats;
// unsigned int phymode;
int mode;
int channel;
u8 bssid[ETH_ALEN];
u8 mac_addr[ETH_ALEN];
u8 revid;
struct ieee80211_supported_band band;
};
#define AGNX_CHAINS_MAX 6
#define AGNX_PERIODIC_DELAY 60000 /* unit: ms */
#define LOCAL_STAID 0 /* the station entry for the card itself */
#define BSSID_STAID 1 /* the station entry for the bsssid AP */
#define spi_delay() udelay(40)
#define eeprom_delay() udelay(40)
#define routing_table_delay() udelay(50)
/* PDU pool MEM region #2 */
#define AGNX_PDUPOOL 0x40000 /* PDU pool */
#define AGNX_PDUPOOL_SIZE 0x8000 /* PDU pool size*/
#define AGNX_PDU_TX_WQ 0x41000 /* PDU list TX workqueue */
#define AGNX_PDU_FREE 0x41800 /* Free Pool */
#define PDU_SIZE 0x80 /* Free Pool node size */
#define PDU_FREE_CNT 0xd0 /* Free pool node count */
/* RF stuffs */
extern void rf_chips_init(struct agnx_priv *priv);
extern void spi_rc_write(void __iomem *mem_region, u32 chip_ids, u32 sw);
extern void calibrate_oscillator(struct agnx_priv *priv);
extern void do_calibration(struct agnx_priv *priv);
extern void antenna_calibrate(struct agnx_priv *priv);
extern void __antenna_calibrate(struct agnx_priv *priv);
extern void print_offsets(struct agnx_priv *priv);
extern int agnx_set_channel(struct agnx_priv *priv, unsigned int channel);
#endif /* AGNX_H_ */
#ifndef AGNX_DEBUG_H_
#define AGNX_DEBUG_H_
#include "agnx.h"
#include "phy.h"
#include "sta.h"
#include "xmit.h"
#define AGNX_TRACE printk(KERN_ERR PFX "function:%s line:%d\n", __func__, __LINE__)
#define PRINTK_LE16(prefix, var) printk(KERN_DEBUG PFX #prefix ": " #var " 0x%.4x\n", le16_to_cpu(var))
#define PRINTK_LE32(prefix, var) printk(KERN_DEBUG PFX #prefix ": " #var " 0x%.8x\n", le32_to_cpu(var))
#define PRINTK_U8(prefix, var) printk(KERN_DEBUG PFX #prefix ": " #var " 0x%.2x\n", var)
#define PRINTK_BE16(prefix, var) printk(KERN_DEBUG PFX #prefix ": " #var " 0x%.4x\n", be16_to_cpu(var))
#define PRINTK_BE32(prefix, var) printk(KERN_DEBUG PFX #prefix ": " #var " 0x%.8x\n", be32_to_cpu(var))
#define PRINTK_BITS(prefix, field) printk(KERN_DEBUG PFX #prefix ": " #field ": 0x%x\n", (reg & field) >> field##_SHIFT)
static inline void agnx_bug(char *reason)
{
printk(KERN_ERR PFX "%s\n", reason);
BUG();
}
static inline void agnx_print_desc(struct agnx_desc *desc)
{
u32 reg = be32_to_cpu(desc->frag);
PRINTK_BITS(DESC, PACKET_LEN);
if (reg & FIRST_FRAG) {
PRINTK_BITS(DESC, FIRST_PACKET_MASK);
PRINTK_BITS(DESC, FIRST_RESERV2);
PRINTK_BITS(DESC, FIRST_TKIP_ERROR);
PRINTK_BITS(DESC, FIRST_TKIP_PACKET);
PRINTK_BITS(DESC, FIRST_RESERV1);
PRINTK_BITS(DESC, FIRST_FRAG_LEN);
} else {
PRINTK_BITS(DESC, SUB_RESERV2);
PRINTK_BITS(DESC, SUB_TKIP_ERROR);
PRINTK_BITS(DESC, SUB_TKIP_PACKET);
PRINTK_BITS(DESC, SUB_RESERV1);
PRINTK_BITS(DESC, SUB_FRAG_LEN);
}
PRINTK_BITS(DESC, FIRST_FRAG);
PRINTK_BITS(DESC, LAST_FRAG);
PRINTK_BITS(DESC, OWNER);
}
static inline void dump_ieee80211b_phy_hdr(__be32 _11b0, __be32 _11b1)
{
}
static inline void agnx_print_hdr(struct agnx_hdr *hdr)
{
u32 reg;
int i;
reg = be32_to_cpu(hdr->reg0);
PRINTK_BITS(HDR, RTS);
PRINTK_BITS(HDR, MULTICAST);
PRINTK_BITS(HDR, ACK);
PRINTK_BITS(HDR, TM);
PRINTK_BITS(HDR, RELAY);
PRINTK_BITS(HDR, REVISED_FCS);
PRINTK_BITS(HDR, NEXT_BUFFER_ADDR);
reg = be32_to_cpu(hdr->reg1);
PRINTK_BITS(HDR, MAC_HDR_LEN);
PRINTK_BITS(HDR, DURATION_OVERIDE);
PRINTK_BITS(HDR, PHY_HDR_OVERIDE);
PRINTK_BITS(HDR, CRC_FAIL);
PRINTK_BITS(HDR, SEQUENCE_NUMBER);
PRINTK_BITS(HDR, BUFF_HEAD_ADDR);
reg = be32_to_cpu(hdr->reg2);
PRINTK_BITS(HDR, PDU_COUNT);
PRINTK_BITS(HDR, WEP_KEY);
PRINTK_BITS(HDR, USES_WEP_KEY);
PRINTK_BITS(HDR, KEEP_ALIVE);
PRINTK_BITS(HDR, BUFF_TAIL_ADDR);
reg = be32_to_cpu(hdr->reg3);
PRINTK_BITS(HDR, CTS_11G);
PRINTK_BITS(HDR, RTS_11G);
PRINTK_BITS(HDR, FRAG_SIZE);
PRINTK_BITS(HDR, PAYLOAD_LEN);
PRINTK_BITS(HDR, FRAG_NUM);
reg = be32_to_cpu(hdr->reg4);
PRINTK_BITS(HDR, RELAY_STAID);
PRINTK_BITS(HDR, STATION_ID);
PRINTK_BITS(HDR, WORKQUEUE_ID);
reg = be32_to_cpu(hdr->reg5);
/* printf the route flag */
PRINTK_BITS(HDR, ROUTE_HOST);
PRINTK_BITS(HDR, ROUTE_CARD_CPU);
PRINTK_BITS(HDR, ROUTE_ENCRYPTION);
PRINTK_BITS(HDR, ROUTE_TX);
PRINTK_BITS(HDR, ROUTE_RX1);
PRINTK_BITS(HDR, ROUTE_RX2);
PRINTK_BITS(HDR, ROUTE_COMPRESSION);
PRINTK_BE32(HDR, hdr->_11g0);
PRINTK_BE32(HDR, hdr->_11g1);
PRINTK_BE32(HDR, hdr->_11b0);
PRINTK_BE32(HDR, hdr->_11b1);
dump_ieee80211b_phy_hdr(hdr->_11b0, hdr->_11b1);
/* Fixme */
for (i = 0; i < ARRAY_SIZE(hdr->mac_hdr); i++) {
if (i == 0)
printk(KERN_DEBUG PFX "IEEE80211 HDR: ");
printk("%.2x ", hdr->mac_hdr[i]);
if (i + 1 == ARRAY_SIZE(hdr->mac_hdr))
printk("\n");
}
PRINTK_BE16(HDR, hdr->rts_duration);
PRINTK_BE16(HDR, hdr->last_duration);
PRINTK_BE16(HDR, hdr->sec_last_duration);
PRINTK_BE16(HDR, hdr->other_duration);
PRINTK_BE16(HDR, hdr->tx_other_duration);
PRINTK_BE16(HDR, hdr->last_11g_len);
PRINTK_BE16(HDR, hdr->other_11g_len);
PRINTK_BE16(HDR, hdr->last_11b_len);
PRINTK_BE16(HDR, hdr->other_11b_len);
/* FIXME */
reg = be16_to_cpu(hdr->reg6);
PRINTK_BITS(HDR, MBF);
PRINTK_BITS(HDR, RSVD4);
PRINTK_BE16(HDR, hdr->rx_frag_stat);
PRINTK_BE32(HDR, hdr->time_stamp);
PRINTK_BE32(HDR, hdr->phy_stats_hi);
PRINTK_BE32(HDR, hdr->phy_stats_lo);
PRINTK_BE32(HDR, hdr->mic_key0);
PRINTK_BE32(HDR, hdr->mic_key1);
} /* agnx_print_hdr */
static inline void agnx_print_rx_hdr(struct agnx_hdr *hdr)
{
agnx_print_hdr(hdr);
PRINTK_BE16(HDR, hdr->rx.rx_packet_duration);
PRINTK_BE16(HDR, hdr->rx.replay_cnt);
PRINTK_U8(HDR, hdr->rx_channel);
}
static inline void agnx_print_tx_hdr(struct agnx_hdr *hdr)
{
agnx_print_hdr(hdr);
PRINTK_U8(HDR, hdr->tx.long_retry_limit);
PRINTK_U8(HDR, hdr->tx.short_retry_limit);
PRINTK_U8(HDR, hdr->tx.long_retry_cnt);
PRINTK_U8(HDR, hdr->tx.short_retry_cnt);
PRINTK_U8(HDR, hdr->rx_channel);
}
static inline void
agnx_print_sta_power(struct agnx_priv *priv, unsigned int sta_idx)
{
struct agnx_sta_power power;
u32 reg;
get_sta_power(priv, &power, sta_idx);
reg = le32_to_cpu(power.reg);
PRINTK_BITS(STA_POWER, SIGNAL);
PRINTK_BITS(STA_POWER, RATE);
PRINTK_BITS(STA_POWER, TIFS);
PRINTK_BITS(STA_POWER, EDCF);
PRINTK_BITS(STA_POWER, CHANNEL_BOND);
PRINTK_BITS(STA_POWER, PHY_MODE);
PRINTK_BITS(STA_POWER, POWER_LEVEL);
PRINTK_BITS(STA_POWER, NUM_TRANSMITTERS);
}
static inline void
agnx_print_sta_tx_wq(struct agnx_priv *priv, unsigned int sta_idx, unsigned int wq_idx)
{
struct agnx_sta_tx_wq tx_wq;
u32 reg;
get_sta_tx_wq(priv, &tx_wq, sta_idx, wq_idx);
reg = le32_to_cpu(tx_wq.reg0);
PRINTK_BITS(STA_TX_WQ, TAIL_POINTER);
PRINTK_BITS(STA_TX_WQ, HEAD_POINTER_LOW);
reg = le32_to_cpu(tx_wq.reg3);
PRINTK_BITS(STA_TX_WQ, HEAD_POINTER_HIGH);
PRINTK_BITS(STA_TX_WQ, ACK_POINTER_LOW);
reg = le32_to_cpu(tx_wq.reg1);
PRINTK_BITS(STA_TX_WQ, ACK_POINTER_HIGH);
PRINTK_BITS(STA_TX_WQ, HEAD_TIMOUT_TAIL_PACK_CNT);
PRINTK_BITS(STA_TX_WQ, ACK_TIMOUT_TAIL_PACK_CNT);
reg = le32_to_cpu(tx_wq.reg2);
PRINTK_BITS(STA_TX_WQ, HEAD_TIMOUT_WIN_LIM_BYTE_CNT);
PRINTK_BITS(STA_TX_WQ, HEAD_TIMOUT_WIN_LIM_FRAG_CNT);
PRINTK_BITS(STA_TX_WQ, WORK_QUEUE_ACK_TYPE);
PRINTK_BITS(STA_TX_WQ, WORK_QUEUE_VALID);
}
static inline void agnx_print_sta_traffic(struct agnx_sta_traffic *traffic)
{
u32 reg;
reg = le32_to_cpu(traffic->reg0);
PRINTK_BITS(STA_TRAFFIC, ACK_TIMOUT_CNT);
PRINTK_BITS(STA_TRAFFIC, TRAFFIC_ACK_TYPE);
PRINTK_BITS(STA_TRAFFIC, NEW_PACKET);
PRINTK_BITS(STA_TRAFFIC, TRAFFIC_VALID);
PRINTK_BITS(STA_TRAFFIC, RX_HDR_DESC_POINTER);
reg = le32_to_cpu(traffic->reg1);
PRINTK_BITS(STA_TRAFFIC, RX_PACKET_TIMESTAMP);
PRINTK_BITS(STA_TRAFFIC, TRAFFIC_RESERVED);
PRINTK_BITS(STA_TRAFFIC, SV);
PRINTK_BITS(STA_TRAFFIC, RX_SEQUENCE_NUM);
PRINTK_LE32(STA_TRAFFIC, traffic->tx_replay_cnt_low);
PRINTK_LE16(STA_TRAFFIC, traffic->tx_replay_cnt_high);
PRINTK_LE16(STA_TRAFFIC, traffic->rx_replay_cnt_high);
PRINTK_LE32(STA_TRAFFIC, traffic->rx_replay_cnt_low);
}
static inline void agnx_print_sta(struct agnx_priv *priv, unsigned int sta_idx)
{
struct agnx_sta station;
struct agnx_sta *sta = &station;
u32 reg;
unsigned int i;
get_sta(priv, sta, sta_idx);
for (i = 0; i < 4; i++)
PRINTK_LE32(STA, sta->tx_session_keys[i]);
for (i = 0; i < 4; i++)
PRINTK_LE32(STA, sta->rx_session_keys[i]);
reg = le32_to_cpu(sta->reg);
PRINTK_BITS(STA, ID_1);
PRINTK_BITS(STA, ID_0);
PRINTK_BITS(STA, ENABLE_CONCATENATION);
PRINTK_BITS(STA, ENABLE_DECOMPRESSION);
PRINTK_BITS(STA, STA_RESERVED);
PRINTK_BITS(STA, EAP);
PRINTK_BITS(STA, ED_NULL);
PRINTK_BITS(STA, ENCRYPTION_POLICY);
PRINTK_BITS(STA, DEFINED_KEY_ID);
PRINTK_BITS(STA, FIXED_KEY);
PRINTK_BITS(STA, KEY_VALID);
PRINTK_BITS(STA, STATION_VALID);
PRINTK_LE32(STA, sta->tx_aes_blks_unicast);
PRINTK_LE32(STA, sta->rx_aes_blks_unicast);
PRINTK_LE16(STA, sta->aes_format_err_unicast_cnt);
PRINTK_LE16(STA, sta->aes_replay_unicast);
PRINTK_LE16(STA, sta->aes_decrypt_err_unicast);
PRINTK_LE16(STA, sta->aes_decrypt_err_default);
PRINTK_LE16(STA, sta->single_retry_packets);
PRINTK_LE16(STA, sta->failed_tx_packets);
PRINTK_LE16(STA, sta->muti_retry_packets);
PRINTK_LE16(STA, sta->ack_timeouts);
PRINTK_LE16(STA, sta->frag_tx_cnt);
PRINTK_LE16(STA, sta->rts_brq_sent);
PRINTK_LE16(STA, sta->tx_packets);
PRINTK_LE16(STA, sta->cts_back_timeout);
PRINTK_LE32(STA, sta->phy_stats_high);
PRINTK_LE32(STA, sta->phy_stats_low);
// for (i = 0; i < 8; i++)
agnx_print_sta_traffic(sta->traffic + 0);
PRINTK_LE16(STA, sta->traffic_class0_frag_success);
PRINTK_LE16(STA, sta->traffic_class1_frag_success);
PRINTK_LE16(STA, sta->traffic_class2_frag_success);
PRINTK_LE16(STA, sta->traffic_class3_frag_success);
PRINTK_LE16(STA, sta->traffic_class4_frag_success);
PRINTK_LE16(STA, sta->traffic_class5_frag_success);
PRINTK_LE16(STA, sta->traffic_class6_frag_success);
PRINTK_LE16(STA, sta->traffic_class7_frag_success);
PRINTK_LE16(STA, sta->num_frag_non_prime_rates);
PRINTK_LE16(STA, sta->ack_timeout_non_prime_rates);
}
static inline void dump_ieee80211_hdr(struct ieee80211_hdr *hdr, char *tag)
{
u16 fctl;
int hdrlen;
DECLARE_MAC_BUF(mac);
fctl = le16_to_cpu(hdr->frame_control);
switch (fctl & IEEE80211_FCTL_FTYPE) {
case IEEE80211_FTYPE_DATA: