Commit ac17a947 authored by Tomas Winkler's avatar Tomas Winkler Committed by David S. Miller

iwlwifi: replacing wording restricted to nic access in iwl-io

This patch replaces wording 'restricted' with more appropriate 'nic access'
NIC access is grabbed to prevent NIC entering power save mode
General cleanup of iwl-io.h
Signed-off-by: default avatarTomas Winkler <tomas.winkler@intel.com>
Signed-off-by: default avatarJohn W. Linville <linville@tuxdriver.com>
parent af7cca2a
......@@ -157,7 +157,7 @@ void iwl_disable_events(struct iwl_priv *priv)
return;
}
ret = iwl_grab_restricted_access(priv);
ret = iwl_grab_nic_access(priv);
if (ret) {
IWL_WARNING("Can not read from adapter at this time.\n");
return;
......@@ -165,18 +165,18 @@ void iwl_disable_events(struct iwl_priv *priv)
disable_ptr = iwl_read_targ_mem(priv, base + (4 * sizeof(u32)));
array_size = iwl_read_targ_mem(priv, base + (5 * sizeof(u32)));
iwl_release_restricted_access(priv);
iwl_release_nic_access(priv);
if (IWL_EVT_DISABLE && (array_size == IWL_EVT_DISABLE_SIZE)) {
IWL_DEBUG_INFO("Disabling selected uCode log events at 0x%x\n",
disable_ptr);
ret = iwl_grab_restricted_access(priv);
ret = iwl_grab_nic_access(priv);
for (i = 0; i < IWL_EVT_DISABLE_SIZE; i++)
iwl_write_targ_mem(priv,
disable_ptr + (i * sizeof(u32)),
evt_disable[i]);
iwl_release_restricted_access(priv);
iwl_release_nic_access(priv);
} else {
IWL_DEBUG_INFO("Selected uCode log events may be disabled\n");
IWL_DEBUG_INFO(" by writing \"1\"s into disable bitmap\n");
......@@ -720,7 +720,7 @@ static int iwl3945_nic_set_pwr_src(struct iwl_priv *priv, int pwr_max)
unsigned long flags;
spin_lock_irqsave(&priv->lock, flags);
rc = iwl_grab_restricted_access(priv);
rc = iwl_grab_nic_access(priv);
if (rc) {
spin_unlock_irqrestore(&priv->lock, flags);
return rc;
......@@ -735,19 +735,19 @@ static int iwl3945_nic_set_pwr_src(struct iwl_priv *priv, int pwr_max)
iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
~APMG_PS_CTRL_MSK_PWR_SRC);
iwl_release_restricted_access(priv);
iwl_release_nic_access(priv);
iwl_poll_bit(priv, CSR_GPIO_IN,
CSR_GPIO_IN_VAL_VAUX_PWR_SRC,
CSR_GPIO_IN_BIT_AUX_POWER, 5000);
} else
iwl_release_restricted_access(priv);
iwl_release_nic_access(priv);
} else {
iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
~APMG_PS_CTRL_MSK_PWR_SRC);
iwl_release_restricted_access(priv);
iwl_release_nic_access(priv);
iwl_poll_bit(priv, CSR_GPIO_IN, CSR_GPIO_IN_VAL_VMAIN_PWR_SRC,
CSR_GPIO_IN_BIT_AUX_POWER, 5000); /* uS */
}
......@@ -762,18 +762,18 @@ static int iwl3945_rx_init(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
unsigned long flags;
spin_lock_irqsave(&priv->lock, flags);
rc = iwl_grab_restricted_access(priv);
rc = iwl_grab_nic_access(priv);
if (rc) {
spin_unlock_irqrestore(&priv->lock, flags);
return rc;
}
iwl_write_restricted(priv, FH_RCSR_RBD_BASE(0), rxq->dma_addr);
iwl_write_restricted(priv, FH_RCSR_RPTR_ADDR(0),
iwl_write_direct32(priv, FH_RCSR_RBD_BASE(0), rxq->dma_addr);
iwl_write_direct32(priv, FH_RCSR_RPTR_ADDR(0),
priv->hw_setting.shared_phys +
offsetof(struct iwl_shared, rx_read_ptr[0]));
iwl_write_restricted(priv, FH_RCSR_WPTR(0), 0);
iwl_write_restricted(priv, FH_RCSR_CONFIG(0),
iwl_write_direct32(priv, FH_RCSR_WPTR(0), 0);
iwl_write_direct32(priv, FH_RCSR_CONFIG(0),
ALM_FH_RCSR_RX_CONFIG_REG_VAL_DMA_CHNL_EN_ENABLE |
ALM_FH_RCSR_RX_CONFIG_REG_VAL_RDRBD_EN_ENABLE |
ALM_FH_RCSR_RX_CONFIG_REG_BIT_WR_STTS_EN |
......@@ -784,9 +784,9 @@ static int iwl3945_rx_init(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
ALM_FH_RCSR_RX_CONFIG_REG_VAL_MSG_MODE_FH);
/* fake read to flush all prev I/O */
iwl_read_restricted(priv, FH_RSSR_CTRL);
iwl_read_direct32(priv, FH_RSSR_CTRL);
iwl_release_restricted_access(priv);
iwl_release_nic_access(priv);
spin_unlock_irqrestore(&priv->lock, flags);
return 0;
......@@ -798,7 +798,7 @@ static int iwl3945_tx_reset(struct iwl_priv *priv)
unsigned long flags;
spin_lock_irqsave(&priv->lock, flags);
rc = iwl_grab_restricted_access(priv);
rc = iwl_grab_nic_access(priv);
if (rc) {
spin_unlock_irqrestore(&priv->lock, flags);
return rc;
......@@ -818,10 +818,10 @@ static int iwl3945_tx_reset(struct iwl_priv *priv)
iwl_write_prph(priv, SCD_TXF4MF_REG, 0x000004);
iwl_write_prph(priv, SCD_TXF5MF_REG, 0x000005);
iwl_write_restricted(priv, FH_TSSR_CBB_BASE,
iwl_write_direct32(priv, FH_TSSR_CBB_BASE,
priv->hw_setting.shared_phys);
iwl_write_restricted(priv, FH_TSSR_MSG_CONFIG,
iwl_write_direct32(priv, FH_TSSR_MSG_CONFIG,
ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TXPD_ON |
ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_TXPD_ON |
ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_MAX_FRAG_SIZE_128B |
......@@ -830,7 +830,7 @@ static int iwl3945_tx_reset(struct iwl_priv *priv)
ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RSP_WAIT_TH |
ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_RSP_WAIT_TH);
iwl_release_restricted_access(priv);
iwl_release_nic_access(priv);
spin_unlock_irqrestore(&priv->lock, flags);
return 0;
......@@ -896,7 +896,7 @@ int iwl_hw_nic_init(struct iwl_priv *priv)
return rc;
}
rc = iwl_grab_restricted_access(priv);
rc = iwl_grab_nic_access(priv);
if (rc) {
spin_unlock_irqrestore(&priv->lock, flags);
return rc;
......@@ -907,7 +907,7 @@ int iwl_hw_nic_init(struct iwl_priv *priv)
udelay(20);
iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
iwl_release_restricted_access(priv);
iwl_release_nic_access(priv);
spin_unlock_irqrestore(&priv->lock, flags);
/* Determine HW type */
......@@ -998,13 +998,13 @@ int iwl_hw_nic_init(struct iwl_priv *priv)
iwl_rx_queue_update_write_ptr(priv, rxq);
*/
rc = iwl_grab_restricted_access(priv);
rc = iwl_grab_nic_access(priv);
if (rc) {
spin_unlock_irqrestore(&priv->lock, flags);
return rc;
}
iwl_write_restricted(priv, FH_RCSR_WPTR(0), rxq->write & ~7);
iwl_release_restricted_access(priv);
iwl_write_direct32(priv, FH_RCSR_WPTR(0), rxq->write & ~7);
iwl_release_nic_access(priv);
spin_unlock_irqrestore(&priv->lock, flags);
......@@ -1037,7 +1037,7 @@ void iwl_hw_txq_ctx_stop(struct iwl_priv *priv)
unsigned long flags;
spin_lock_irqsave(&priv->lock, flags);
if (iwl_grab_restricted_access(priv)) {
if (iwl_grab_nic_access(priv)) {
spin_unlock_irqrestore(&priv->lock, flags);
iwl_hw_txq_ctx_free(priv);
return;
......@@ -1048,13 +1048,13 @@ void iwl_hw_txq_ctx_stop(struct iwl_priv *priv)
/* reset TFD queues */
for (queue = TFD_QUEUE_MIN; queue < TFD_QUEUE_MAX; queue++) {
iwl_write_restricted(priv, FH_TCSR_CONFIG(queue), 0x0);
iwl_poll_restricted_bit(priv, FH_TSSR_TX_STATUS,
iwl_write_direct32(priv, FH_TCSR_CONFIG(queue), 0x0);
iwl_poll_direct_bit(priv, FH_TSSR_TX_STATUS,
ALM_FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(queue),
1000);
}
iwl_release_restricted_access(priv);
iwl_release_nic_access(priv);
spin_unlock_irqrestore(&priv->lock, flags);
iwl_hw_txq_ctx_free(priv);
......@@ -1108,7 +1108,7 @@ int iwl_hw_nic_reset(struct iwl_priv *priv)
CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
rc = iwl_grab_restricted_access(priv);
rc = iwl_grab_nic_access(priv);
if (!rc) {
iwl_write_prph(priv, APMG_CLK_CTRL_REG,
APMG_CLK_VAL_BSM_CLK_RQT);
......@@ -1133,7 +1133,7 @@ int iwl_hw_nic_reset(struct iwl_priv *priv)
udelay(5);
iwl_clear_bits_prph(priv, APMG_PS_CTRL_REG,
APMG_PS_CTRL_VAL_RESET_REQ);
iwl_release_restricted_access(priv);
iwl_release_nic_access(priv);
}
/* Clear the 'host command active' bit... */
......@@ -2096,18 +2096,18 @@ int iwl_hw_rxq_stop(struct iwl_priv *priv)
unsigned long flags;
spin_lock_irqsave(&priv->lock, flags);
rc = iwl_grab_restricted_access(priv);
rc = iwl_grab_nic_access(priv);
if (rc) {
spin_unlock_irqrestore(&priv->lock, flags);
return rc;
}
iwl_write_restricted(priv, FH_RCSR_CONFIG(0), 0);
rc = iwl_poll_restricted_bit(priv, FH_RSSR_STATUS, (1 << 24), 1000);
iwl_write_direct32(priv, FH_RCSR_CONFIG(0), 0);
rc = iwl_poll_direct_bit(priv, FH_RSSR_STATUS, (1 << 24), 1000);
if (rc < 0)
IWL_ERROR("Can't stop Rx DMA.\n");
iwl_release_restricted_access(priv);
iwl_release_nic_access(priv);
spin_unlock_irqrestore(&priv->lock, flags);
return 0;
......@@ -2124,21 +2124,21 @@ int iwl_hw_tx_queue_init(struct iwl_priv *priv, struct iwl_tx_queue *txq)
shared_data->tx_base_ptr[txq_id] = cpu_to_le32((u32)txq->q.dma_addr);
spin_lock_irqsave(&priv->lock, flags);
rc = iwl_grab_restricted_access(priv);
rc = iwl_grab_nic_access(priv);
if (rc) {
spin_unlock_irqrestore(&priv->lock, flags);
return rc;
}
iwl_write_restricted(priv, FH_CBCC_CTRL(txq_id), 0);
iwl_write_restricted(priv, FH_CBCC_BASE(txq_id), 0);
iwl_write_direct32(priv, FH_CBCC_CTRL(txq_id), 0);
iwl_write_direct32(priv, FH_CBCC_BASE(txq_id), 0);
iwl_write_restricted(priv, FH_TCSR_CONFIG(txq_id),
iwl_write_direct32(priv, FH_TCSR_CONFIG(txq_id),
ALM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT |
ALM_FH_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF |
ALM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD |
ALM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL |
ALM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE);
iwl_release_restricted_access(priv);
iwl_release_nic_access(priv);
/* fake read to flush all prev. writes */
iwl_read32(priv, FH_TSSR_CBB_BASE);
......
......@@ -139,20 +139,20 @@ int iwl_hw_rxq_stop(struct iwl_priv *priv)
unsigned long flags;
spin_lock_irqsave(&priv->lock, flags);
rc = iwl_grab_restricted_access(priv);
rc = iwl_grab_nic_access(priv);
if (rc) {
spin_unlock_irqrestore(&priv->lock, flags);
return rc;
}
/* stop HW */
iwl_write_restricted(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
rc = iwl_poll_restricted_bit(priv, FH_MEM_RSSR_RX_STATUS_REG,
iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
rc = iwl_poll_direct_bit(priv, FH_MEM_RSSR_RX_STATUS_REG,
(1 << 24), 1000);
if (rc < 0)
IWL_ERROR("Can't stop Rx DMA.\n");
iwl_release_restricted_access(priv);
iwl_release_nic_access(priv);
spin_unlock_irqrestore(&priv->lock, flags);
return 0;
......@@ -196,7 +196,7 @@ static int iwl4965_nic_set_pwr_src(struct iwl_priv *priv, int pwr_max)
unsigned long flags;
spin_lock_irqsave(&priv->lock, flags);
ret = iwl_grab_restricted_access(priv);
ret = iwl_grab_nic_access(priv);
if (ret) {
spin_unlock_irqrestore(&priv->lock, flags);
return ret;
......@@ -217,7 +217,7 @@ static int iwl4965_nic_set_pwr_src(struct iwl_priv *priv, int pwr_max)
APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
~APMG_PS_CTRL_MSK_PWR_SRC);
iwl_release_restricted_access(priv);
iwl_release_nic_access(priv);
spin_unlock_irqrestore(&priv->lock, flags);
return ret;
......@@ -229,24 +229,24 @@ static int iwl4965_rx_init(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
unsigned long flags;
spin_lock_irqsave(&priv->lock, flags);
rc = iwl_grab_restricted_access(priv);
rc = iwl_grab_nic_access(priv);
if (rc) {
spin_unlock_irqrestore(&priv->lock, flags);
return rc;
}
/* stop HW */
iwl_write_restricted(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
iwl_write_restricted(priv, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0);
iwl_write_restricted(priv, FH_RSCSR_CHNL0_RBDCB_BASE_REG,
iwl_write_direct32(priv, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0);
iwl_write_direct32(priv, FH_RSCSR_CHNL0_RBDCB_BASE_REG,
rxq->dma_addr >> 8);
iwl_write_restricted(priv, FH_RSCSR_CHNL0_STTS_WPTR_REG,
iwl_write_direct32(priv, FH_RSCSR_CHNL0_STTS_WPTR_REG,
(priv->hw_setting.shared_phys +
offsetof(struct iwl_shared, val0)) >> 4);
iwl_write_restricted(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG,
iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG,
FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL |
FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL |
IWL_FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K |
......@@ -258,7 +258,7 @@ static int iwl4965_rx_init(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
* iwl_write32(priv,CSR_INT_COAL_REG,0);
*/
iwl_release_restricted_access(priv);
iwl_release_nic_access(priv);
spin_unlock_irqrestore(&priv->lock, flags);
return 0;
......@@ -270,13 +270,13 @@ static int iwl4965_kw_init(struct iwl_priv *priv)
int rc;
spin_lock_irqsave(&priv->lock, flags);
rc = iwl_grab_restricted_access(priv);
rc = iwl_grab_nic_access(priv);
if (rc)
goto out;
iwl_write_restricted(priv, IWL_FH_KW_MEM_ADDR_REG,
iwl_write_direct32(priv, IWL_FH_KW_MEM_ADDR_REG,
priv->kw.dma_addr >> 4);
iwl_release_restricted_access(priv);
iwl_release_nic_access(priv);
out:
spin_unlock_irqrestore(&priv->lock, flags);
return rc;
......@@ -375,7 +375,7 @@ static int iwl4965_txq_ctx_reset(struct iwl_priv *priv)
spin_lock_irqsave(&priv->lock, flags);
rc = iwl_grab_restricted_access(priv);
rc = iwl_grab_nic_access(priv);
if (unlikely(rc)) {
IWL_ERROR("TX reset failed");
spin_unlock_irqrestore(&priv->lock, flags);
......@@ -383,7 +383,7 @@ static int iwl4965_txq_ctx_reset(struct iwl_priv *priv)
}
iwl_write_prph(priv, SCD_TXFACT, 0);
iwl_release_restricted_access(priv);
iwl_release_nic_access(priv);
spin_unlock_irqrestore(&priv->lock, flags);
rc = iwl4965_kw_init(priv);
......@@ -441,7 +441,7 @@ int iwl_hw_nic_init(struct iwl_priv *priv)
return rc;
}
rc = iwl_grab_restricted_access(priv);
rc = iwl_grab_nic_access(priv);
if (rc) {
spin_unlock_irqrestore(&priv->lock, flags);
return rc;
......@@ -459,7 +459,7 @@ int iwl_hw_nic_init(struct iwl_priv *priv)
iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
iwl_release_restricted_access(priv);
iwl_release_nic_access(priv);
iwl_write32(priv, CSR_INT_COALESCING, 512 / 32);
spin_unlock_irqrestore(&priv->lock, flags);
......@@ -505,7 +505,7 @@ int iwl_hw_nic_init(struct iwl_priv *priv)
CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI |
CSR_HW_IF_CONFIG_REG_BIT_MAC_SI);
rc = iwl_grab_restricted_access(priv);
rc = iwl_grab_nic_access(priv);
if (rc < 0) {
spin_unlock_irqrestore(&priv->lock, flags);
IWL_DEBUG_INFO("Failed to init the card\n");
......@@ -519,7 +519,7 @@ int iwl_hw_nic_init(struct iwl_priv *priv)
iwl_clear_bits_prph(priv, APMG_PS_CTRL_REG,
APMG_PS_CTRL_VAL_RESET_REQ);
iwl_release_restricted_access(priv);
iwl_release_nic_access(priv);
spin_unlock_irqrestore(&priv->lock, flags);
iwl_hw_card_show_info(priv);
......@@ -603,18 +603,18 @@ void iwl_hw_txq_ctx_stop(struct iwl_priv *priv)
/* reset TFD queues */
for (txq_id = 0; txq_id < priv->hw_setting.max_txq_num; txq_id++) {
spin_lock_irqsave(&priv->lock, flags);
if (iwl_grab_restricted_access(priv)) {
if (iwl_grab_nic_access(priv)) {
spin_unlock_irqrestore(&priv->lock, flags);
continue;
}
iwl_write_restricted(priv,
iwl_write_direct32(priv,
IWL_FH_TCSR_CHNL_TX_CONFIG_REG(txq_id),
0x0);
iwl_poll_restricted_bit(priv, IWL_FH_TSSR_TX_STATUS_REG,
iwl_poll_direct_bit(priv, IWL_FH_TSSR_TX_STATUS_REG,
IWL_FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE
(txq_id), 200);
iwl_release_restricted_access(priv);
iwl_release_nic_access(priv);
spin_unlock_irqrestore(&priv->lock, flags);
}
......@@ -641,7 +641,7 @@ int iwl_hw_nic_reset(struct iwl_priv *priv)
udelay(10);
rc = iwl_grab_restricted_access(priv);
rc = iwl_grab_nic_access(priv);
if (!rc) {
iwl_write_prph(priv, APMG_CLK_EN_REG,
APMG_CLK_VAL_DMA_CLK_RQT |
......@@ -652,7 +652,7 @@ int iwl_hw_nic_reset(struct iwl_priv *priv)
iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
iwl_release_restricted_access(priv);
iwl_release_nic_access(priv);
}
clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
......@@ -1581,7 +1581,7 @@ static void iwl4965_bg_txpower_work(struct work_struct *work)
*/
static void iwl4965_set_wr_ptrs(struct iwl_priv *priv, int txq_id, u32 index)
{
iwl_write_restricted(priv, HBUS_TARG_WRPTR,
iwl_write_direct32(priv, HBUS_TARG_WRPTR,
(index & 0xff) | (txq_id << 8));
iwl_write_prph(priv, SCD_QUEUE_RDPTR(txq_id), index);
}
......@@ -1648,7 +1648,7 @@ int iwl4965_alive_notify(struct iwl_priv *priv)
priv->chain_noise_data.delta_gain_code[i] =
CHAIN_NOISE_DELTA_GAIN_INIT_VAL;
#endif /* CONFIG_IWLWIFI_SENSITIVITY*/
rc = iwl_grab_restricted_access(priv);
rc = iwl_grab_nic_access(priv);
if (rc) {
spin_unlock_irqrestore(&priv->lock, flags);
return rc;
......@@ -1671,7 +1671,7 @@ int iwl4965_alive_notify(struct iwl_priv *priv)
/* initiate the queues */
for (i = 0; i < priv->hw_setting.max_txq_num; i++) {
iwl_write_prph(priv, SCD_QUEUE_RDPTR(i), 0);
iwl_write_restricted(priv, HBUS_TARG_WRPTR, 0 | (i << 8));
iwl_write_direct32(priv, HBUS_TARG_WRPTR, 0 | (i << 8));
iwl_write_targ_mem(priv, priv->scd_base_addr +
SCD_CONTEXT_QUEUE_OFFSET(i),
(SCD_WIN_SIZE <<
......@@ -1699,7 +1699,7 @@ int iwl4965_alive_notify(struct iwl_priv *priv)
iwl4965_tx_queue_set_status(priv, &priv->txq[i], ac, 0);
}
iwl_release_restricted_access(priv);
iwl_release_nic_access(priv);
spin_unlock_irqrestore(&priv->lock, flags);
return 0;
......@@ -2688,19 +2688,19 @@ int iwl_hw_tx_queue_init(struct iwl_priv *priv, struct iwl_tx_queue *txq)
int txq_id = txq->q.id;
spin_lock_irqsave(&priv->lock, flags);
rc = iwl_grab_restricted_access(priv);
rc = iwl_grab_nic_access(priv);
if (rc) {
spin_unlock_irqrestore(&priv->lock, flags);
return rc;
}
iwl_write_restricted(priv, FH_MEM_CBBC_QUEUE(txq_id),
iwl_write_direct32(priv, FH_MEM_CBBC_QUEUE(txq_id),
txq->q.dma_addr >> 8);
iwl_write_restricted(
iwl_write_direct32(
priv, IWL_FH_TCSR_CHNL_TX_CONFIG_REG(txq_id),
IWL_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
IWL_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL);
iwl_release_restricted_access(priv);
iwl_release_nic_access(priv);
spin_unlock_irqrestore(&priv->lock, flags);
return 0;
......@@ -4188,7 +4188,7 @@ static int iwl4965_tx_queue_agg_enable(struct iwl_priv *priv, int txq_id,
iwl_sta_modify_enable_tid_tx(priv, sta_id, tid);
spin_lock_irqsave(&priv->lock, flags);
rc = iwl_grab_restricted_access(priv);
rc = iwl_grab_nic_access(priv);
if (rc) {
spin_unlock_irqrestore(&priv->lock, flags);
return rc;
......@@ -4221,7 +4221,7 @@ static int iwl4965_tx_queue_agg_enable(struct iwl_priv *priv, int txq_id,
iwl4965_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 1);
iwl_release_restricted_access(priv);
iwl_release_nic_access(priv);
spin_unlock_irqrestore(&priv->lock, flags);
return 0;
......@@ -4243,7 +4243,7 @@ static int iwl4965_tx_queue_agg_disable(struct iwl_priv *priv, u16 txq_id,
}
spin_lock_irqsave(&priv->lock, flags);
rc = iwl_grab_restricted_access(priv);
rc = iwl_grab_nic_access(priv);
if (rc) {
spin_unlock_irqrestore(&priv->lock, flags);
return rc;
......@@ -4262,7 +4262,7 @@ static int iwl4965_tx_queue_agg_disable(struct iwl_priv *priv, u16 txq_id,
iwl4965_txq_ctx_deactivate(priv, txq_id);
iwl4965_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 0);
iwl_release_restricted_access(priv);
iwl_release_nic_access(priv);
spin_unlock_irqrestore(&priv->lock, flags);
return 0;
......
......@@ -42,15 +42,14 @@
* check or debug information is printed when that function is called.
*
* A double __ prefix before an access function means that state is checked
* (in the case of *restricted calls) and the current line number is printed
* in addition to any other debug output.
* and the current line number is printed in addition to any other debug output.
*
* The non-prefixed name is the #define that maps the caller into a
* #define that provides the caller's __LINE__ to the double prefix version.
*
* If you wish to call the function without any debug or state checking,
* you should use the single _ prefix version (as is used by dependent IO
* routines, for example _iwl_read_restricted calls the non-check version of
* routines, for example _iwl_read_direct32 calls the non-check version of
* _iwl_read32.)
*
* These declarations are *extremely* useful in quickly isolating code deltas
......@@ -65,8 +64,7 @@
static inline void __iwl_write32(const char *f, u32 l, struct iwl_priv *iwl,
u32 ofs, u32 val)
{
IWL_DEBUG_IO("write_direct32(0x%08X, 0x%08X) - %s %d\n",
(u32) (ofs), (u32) (val), f, l);
IWL_DEBUG_IO("write32(0x%08X, 0x%08X) - %s %d\n", ofs, val, f, l);
_iwl_write32(iwl, ofs, val);
}
#define iwl_write32(iwl, ofs, val) \
......@@ -106,16 +104,16 @@ static inline int __iwl_poll_bit(const char *f, u32 l,
struct iwl_priv *priv, u32 addr,
u32 bits, u32 mask, int timeout)
{
int rc = _iwl_poll_bit(priv, addr, bits, mask, timeout);
if (unlikely(rc == -ETIMEDOUT))
int ret = _iwl_poll_bit(priv, addr, bits, mask, timeout);
if (unlikely(ret == -ETIMEDOUT))
IWL_DEBUG_IO
("poll_bit(0x%08X, 0x%08X, 0x%08X) - timedout - %s %d\n",
addr, bits, mask, f, l);
else
IWL_DEBUG_IO
("poll_bit(0x%08X, 0x%08X, 0x%08X) = 0x%08X - %s %d\n",
addr, bits, mask, rc, f, l);
return rc;
addr, bits, mask, ret, f, l);
return ret;
}
#define iwl_poll_bit(iwl, addr, bits, mask, timeout) \
__iwl_poll_bit(__FILE__, __LINE__, iwl, addr, bits, mask, timeout)
......@@ -157,9 +155,9 @@ static inline void __iwl_clear_bit(const char *f, u32 l,
#define iwl_clear_bit(p, r, m) _iwl_clear_bit(p, r, m)
#endif
static inline int _iwl_grab_restricted_access(struct iwl_priv *priv)
static inline int _iwl_grab_nic_access(struct iwl_priv *priv)
{
int rc;
int ret;
u32 gp_ctl;
#ifdef CONFIG_IWLWIFI_DEBUG
......@@ -184,11 +182,11 @@ static inline int _iwl_grab_restricted_access(struct iwl_priv *priv)
/* this bit wakes up the NIC */
_iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
rc = _iwl_poll_bit(priv, CSR_GP_CNTRL,
ret = _iwl_poll_bit(priv, CSR_GP_CNTRL,
CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN,
(CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY |
CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), 50);
if (rc < 0) {
if (ret < 0) {
IWL_ERROR("MAC is in deep sleep!\n");
return -EIO;
}
......@@ -200,25 +198,24 @@ static inline int _iwl_grab_restricted_access(struct iwl_priv *priv)
}
#ifdef CONFIG_IWLWIFI_DEBUG
static inline int __iwl_grab_restricted_access(const char *f, u32 l,
static inline int __iwl_grab_nic_access(const char *f, u32 l,
struct iwl_priv *priv)
{
if (atomic_read(&priv->restrict_refcnt))
IWL_DEBUG_INFO("Grabbing access while already held at "
"line %d.\n", l);
IWL_DEBUG_IO("grabbing restricted access - %s %d\n", f, l);