Commit 99673d9b authored by Bruce Allan's avatar Bruce Allan Committed by David S. Miller
Browse files

e1000e: cleanup functions that clear hardware statistics



The e1000_clear_hw_cntrs_*() functions read the registers to clear them.
There is no reason to save the register contents so the temp variable can
be removed.
Signed-off-by: default avatarBruce Allan <bruce.w.allan@intel.com>
Signed-off-by: default avatarJeff Kirsher <jeffrey.t.kirsher@intel.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 3d5e33c9
......@@ -1613,44 +1613,42 @@ static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw)
**/
static void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw)
{
u32 temp;
e1000e_clear_hw_cntrs_base(hw);
temp = er32(PRC64);
temp = er32(PRC127);
temp = er32(PRC255);
temp = er32(PRC511);
temp = er32(PRC1023);
temp = er32(PRC1522);
temp = er32(PTC64);
temp = er32(PTC127);
temp = er32(PTC255);
temp = er32(PTC511);
temp = er32(PTC1023);
temp = er32(PTC1522);
temp = er32(ALGNERRC);
temp = er32(RXERRC);
temp = er32(TNCRS);
temp = er32(CEXTERR);
temp = er32(TSCTC);
temp = er32(TSCTFC);
temp = er32(MGTPRC);
temp = er32(MGTPDC);
temp = er32(MGTPTC);
temp = er32(IAC);
temp = er32(ICRXOC);
temp = er32(ICRXPTC);
temp = er32(ICRXATC);
temp = er32(ICTXPTC);
temp = er32(ICTXATC);
temp = er32(ICTXQEC);
temp = er32(ICTXQMTC);
temp = er32(ICRXDMTC);
er32(PRC64);
er32(PRC127);
er32(PRC255);
er32(PRC511);
er32(PRC1023);
er32(PRC1522);
er32(PTC64);
er32(PTC127);
er32(PTC255);
er32(PTC511);
er32(PTC1023);
er32(PTC1522);
er32(ALGNERRC);
er32(RXERRC);
er32(TNCRS);
er32(CEXTERR);
er32(TSCTC);
er32(TSCTFC);
er32(MGTPRC);
er32(MGTPDC);
er32(MGTPTC);
er32(IAC);
er32(ICRXOC);
er32(ICRXPTC);
er32(ICRXATC);
er32(ICTXPTC);
er32(ICTXATC);
er32(ICTXQEC);
er32(ICTXQMTC);
er32(ICRXDMTC);
}
static struct e1000_mac_operations e82571_mac_ops = {
......
......@@ -1304,44 +1304,42 @@ static s32 e1000_write_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
**/
static void e1000_clear_hw_cntrs_80003es2lan(struct e1000_hw *hw)
{
u32 temp;
e1000e_clear_hw_cntrs_base(hw);
temp = er32(PRC64);
temp = er32(PRC127);
temp = er32(PRC255);
temp = er32(PRC511);
temp = er32(PRC1023);
temp = er32(PRC1522);
temp = er32(PTC64);
temp = er32(PTC127);
temp = er32(PTC255);
temp = er32(PTC511);
temp = er32(PTC1023);
temp = er32(PTC1522);
temp = er32(ALGNERRC);
temp = er32(RXERRC);
temp = er32(TNCRS);
temp = er32(CEXTERR);
temp = er32(TSCTC);
temp = er32(TSCTFC);
temp = er32(MGTPRC);
temp = er32(MGTPDC);
temp = er32(MGTPTC);
temp = er32(IAC);
temp = er32(ICRXOC);
temp = er32(ICRXPTC);
temp = er32(ICRXATC);
temp = er32(ICTXPTC);
temp = er32(ICTXATC);
temp = er32(ICTXQEC);
temp = er32(ICTXQMTC);
temp = er32(ICRXDMTC);
er32(PRC64);
er32(PRC127);
er32(PRC255);
er32(PRC511);
er32(PRC1023);
er32(PRC1522);
er32(PTC64);
er32(PTC127);
er32(PTC255);
er32(PTC511);
er32(PTC1023);
er32(PTC1522);
er32(ALGNERRC);
er32(RXERRC);
er32(TNCRS);
er32(CEXTERR);
er32(TSCTC);
er32(TSCTFC);
er32(MGTPRC);
er32(MGTPDC);
er32(MGTPTC);
er32(IAC);
er32(ICRXOC);
er32(ICRXPTC);
er32(ICRXATC);
er32(ICTXPTC);
er32(ICTXATC);
er32(ICTXQEC);
er32(ICTXQMTC);
er32(ICRXDMTC);
}
static struct e1000_mac_operations es2_mac_ops = {
......
......@@ -3402,24 +3402,23 @@ static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw)
**/
static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw)
{
u32 temp;
u16 phy_data;
e1000e_clear_hw_cntrs_base(hw);
temp = er32(ALGNERRC);
temp = er32(RXERRC);
temp = er32(TNCRS);
temp = er32(CEXTERR);
temp = er32(TSCTC);
temp = er32(TSCTFC);
er32(ALGNERRC);
er32(RXERRC);
er32(TNCRS);
er32(CEXTERR);
er32(TSCTC);
er32(TSCTFC);
temp = er32(MGTPRC);
temp = er32(MGTPDC);
temp = er32(MGTPTC);
er32(MGTPRC);
er32(MGTPDC);
er32(MGTPTC);
temp = er32(IAC);
temp = er32(ICRXOC);
er32(IAC);
er32(ICRXOC);
/* Clear PHY statistics registers */
if ((hw->phy.type == e1000_phy_82578) ||
......
......@@ -295,45 +295,43 @@ void e1000e_update_mc_addr_list_generic(struct e1000_hw *hw,
**/
void e1000e_clear_hw_cntrs_base(struct e1000_hw *hw)
{
u32 temp;
temp = er32(CRCERRS);
temp = er32(SYMERRS);
temp = er32(MPC);
temp = er32(SCC);
temp = er32(ECOL);
temp = er32(MCC);
temp = er32(LATECOL);
temp = er32(COLC);
temp = er32(DC);
temp = er32(SEC);
temp = er32(RLEC);
temp = er32(XONRXC);
temp = er32(XONTXC);
temp = er32(XOFFRXC);
temp = er32(XOFFTXC);
temp = er32(FCRUC);
temp = er32(GPRC);
temp = er32(BPRC);
temp = er32(MPRC);
temp = er32(GPTC);
temp = er32(GORCL);
temp = er32(GORCH);
temp = er32(GOTCL);
temp = er32(GOTCH);
temp = er32(RNBC);
temp = er32(RUC);
temp = er32(RFC);
temp = er32(ROC);
temp = er32(RJC);
temp = er32(TORL);
temp = er32(TORH);
temp = er32(TOTL);
temp = er32(TOTH);
temp = er32(TPR);
temp = er32(TPT);
temp = er32(MPTC);
temp = er32(BPTC);
er32(CRCERRS);
er32(SYMERRS);
er32(MPC);
er32(SCC);
er32(ECOL);
er32(MCC);
er32(LATECOL);
er32(COLC);
er32(DC);
er32(SEC);
er32(RLEC);
er32(XONRXC);
er32(XONTXC);
er32(XOFFRXC);
er32(XOFFTXC);
er32(FCRUC);
er32(GPRC);
er32(BPRC);
er32(MPRC);
er32(GPTC);
er32(GORCL);
er32(GORCH);
er32(GOTCL);
er32(GOTCH);
er32(RNBC);
er32(RUC);
er32(RFC);
er32(ROC);
er32(RJC);
er32(TORL);
er32(TORH);
er32(TOTL);
er32(TOTH);
er32(TPR);
er32(TPT);
er32(MPTC);
er32(BPTC);
}
/**
......
Markdown is supported
0% or .
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment