Commit 9267a30d authored by Marc St-Jean's avatar Marc St-Jean Committed by Ralf Baechle

[MIPS] PMC MSP71xx mips common

Patch to add mips common support for the PMC-Sierra MSP71xx devices.
Signed-off-by: default avatarMarc St-Jean <Marc_St-Jean@pmc-sierra.com>
Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent 35832e26
......@@ -250,6 +250,7 @@ config MIPS_SIM
select DMA_NONCOHERENT
select SYS_HAS_EARLY_PRINTK
select IRQ_CPU
select BOOT_RAW
select SYS_HAS_CPU_MIPS32_R1
select SYS_HAS_CPU_MIPS32_R2
select SYS_HAS_EARLY_PRINTK
......@@ -333,6 +334,27 @@ config MACH_VR41XX
select SYS_HAS_CPU_VR41XX
select GENERIC_HARDIRQS_NO__DO_IRQ
config PMC_MSP
bool "PMC-Sierra MSP chipsets"
depends on EXPERIMENTAL
select DMA_NONCOHERENT
select SWAP_IO_SPACE
select NO_EXCEPT_FILL
select BOOT_RAW
select SYS_HAS_CPU_MIPS32_R1
select SYS_HAS_CPU_MIPS32_R2
select SYS_SUPPORTS_32BIT_KERNEL
select SYS_SUPPORTS_BIG_ENDIAN
select SYS_SUPPORTS_KGDB
select IRQ_CPU
select SERIAL_8250
select SERIAL_8250_CONSOLE
help
This adds support for the PMC-Sierra family of Multi-Service
Processor System-On-A-Chips. These parts include a number
of integrated peripherals, interfaces and DSPs in addition to
a variety of MIPS cores.
config PMC_YOSEMITE
bool "PMC-Sierra Yosemite eval board"
select DMA_COHERENT
......@@ -706,6 +728,9 @@ config ARC
config ARCH_MAY_HAVE_PC_FDC
bool
config BOOT_RAW
bool
config DMA_COHERENT
bool
......@@ -812,6 +837,12 @@ config IRQ_CPU_RM7K
config IRQ_CPU_RM9K
bool
config IRQ_MSP_SLP
bool
config IRQ_MSP_CIC
bool
config IRQ_MV64340
bool
......@@ -825,6 +856,9 @@ config MIPS_BOARDS_GEN
config PCI_GT64XXX_PCI0
bool
config NO_EXCEPT_FILL
bool
config MIPS_TX3927
bool
select HAS_TXX9_SERIAL
......@@ -886,6 +920,7 @@ config MIPS_L1_CACHE_SHIFT
int
default "4" if MACH_DECSTATION || SNI_RM
default "7" if SGI_IP27
default "4" if PMC_MSP4200_EVAL
default "5"
config HAVE_STD_PC_SERIAL_PORT
......
......@@ -342,6 +342,14 @@ core-$(CONFIG_MOMENCO_OCELOT) += arch/mips/gt64120/common/ \
cflags-$(CONFIG_MOMENCO_OCELOT) += -Iinclude/asm-mips/mach-ocelot
load-$(CONFIG_MOMENCO_OCELOT) += 0xffffffff80100000
#
# PMC-Sierra MSP SOCs
#
core-$(CONFIG_PMC_MSP) += arch/mips/pmc-sierra/msp71xx/
cflags-$(CONFIG_PMC_MSP) += -Iinclude/asm-mips/pmc-sierra/msp71xx \
-mno-branch-likely
load-$(CONFIG_PMC_MSP) += 0xffffffff80100000
#
# PMC-Sierra Yosemite
#
......@@ -595,7 +603,8 @@ JIFFIES = jiffies_64
endif
AFLAGS += $(cflags-y)
CFLAGS += $(cflags-y)
CFLAGS += $(cflags-y) \
-D"VMLINUX_LOAD_ADDRESS=$(load-y)"
LDFLAGS += -m $(ld-emul)
......
......@@ -186,9 +186,29 @@ static inline void check_wait(void)
}
}
static inline void check_errata(void)
{
struct cpuinfo_mips *c = &current_cpu_data;
switch (c->cputype) {
case CPU_34K:
/*
* Erratum "RPS May Cause Incorrect Instruction Execution"
* This code only handles VPE0, any SMP/SMTC/RTOS code
* making use of VPE1 will be responsable for that VPE.
*/
if ((c->processor_id & PRID_REV_MASK) <= PRID_REV_34K_V1_0_2)
write_c0_config7(read_c0_config7() | MIPS_CONF7_RPS);
break;
default:
break;
}
}
void __init check_bugs32(void)
{
check_wait();
check_errata();
}
/*
......
......@@ -16,6 +16,7 @@
#include <linux/init.h>
#include <linux/threads.h>
#include <asm/addrspace.h>
#include <asm/asm.h>
#include <asm/asmmacro.h>
#include <asm/irqflags.h>
......@@ -129,16 +130,18 @@
#endif
.endm
#ifndef CONFIG_NO_EXCEPT_FILL
/*
* Reserved space for exception handlers.
* Necessary for machines which link their kernels at KSEG0.
*/
.fill 0x400
#endif
EXPORT(stext) # used for profiling
EXPORT(_stext)
#ifndef CONFIG_MIPS_SIM
#ifdef CONFIG_BOOT_RAW
/*
* Give us a fighting chance of running if execution beings at the
* kernel load address. This is needed because this platform does
......
......@@ -69,6 +69,7 @@ extern asmlinkage void handle_reserved(void);
extern int fpu_emulator_cop1Handler(struct pt_regs *xcp,
struct mips_fpu_struct *ctx, int has_fpu);
void (*board_watchpoint_handler)(struct pt_regs *regs);
void (*board_be_init)(void);
int (*board_be_handler)(struct pt_regs *regs, int is_fixup);
void (*board_nmi_handler_setup)(void);
......@@ -833,6 +834,11 @@ asmlinkage void do_mdmx(struct pt_regs *regs)
asmlinkage void do_watch(struct pt_regs *regs)
{
if (board_watchpoint_handler) {
(*board_watchpoint_handler)(regs);
return;
}
/*
* We use the watch exception where available to detect stack
* overflows.
......
choice
prompt "PMC-Sierra MSP SOC type"
depends on PMC_MSP
config PMC_MSP4200_EVAL
bool "PMC-Sierra MSP4200 Eval Board"
select IRQ_MSP_SLP
select HW_HAS_PCI
config PMC_MSP4200_GW
bool "PMC-Sierra MSP4200 VoIP Gateway"
select IRQ_MSP_SLP
select HW_HAS_PCI
config PMC_MSP7120_EVAL
bool "PMC-Sierra MSP7120 Eval Board"
select SYS_SUPPORTS_MULTITHREADING
select IRQ_MSP_CIC
select HW_HAS_PCI
config PMC_MSP7120_GW
bool "PMC-Sierra MSP7120 Residential Gateway"
select SYS_SUPPORTS_MULTITHREADING
select IRQ_MSP_CIC
select HW_HAS_PCI
config PMC_MSP7120_FPGA
bool "PMC-Sierra MSP7120 FPGA"
select SYS_SUPPORTS_MULTITHREADING
select IRQ_MSP_CIC
select HW_HAS_PCI
endchoice
menu "Options for PMC-Sierra MSP chipsets"
depends on PMC_MSP
config PMC_MSP_EMBEDDED_ROOTFS
bool "Root filesystem embedded in kernel image"
select MTD
select MTD_BLOCK
select MTD_PMC_MSP_RAMROOT
select MTD_RAM
endmenu
config HYPERTRANSPORT
bool "Hypertransport Support for PMC-Sierra Yosemite"
depends on PMC_YOSEMITE
......@@ -213,6 +213,18 @@
#define MACH_GROUP_LEMOTE 27
#define MACH_LEMOTE_FULONG 0
/*
* Valid machtype for group PMC-MSP
*/
#define MACH_GROUP_MSP 26 /* PMC-Sierra MSP boards/CPUs */
#define MACH_MSP4200_EVAL 0 /* PMC-Sierra MSP4200 Evaluation */
#define MACH_MSP4200_GW 1 /* PMC-Sierra MSP4200 Gateway demo */
#define MACH_MSP4200_FPGA 2 /* PMC-Sierra MSP4200 Emulation */
#define MACH_MSP7120_EVAL 3 /* PMC-Sierra MSP7120 Evaluation */
#define MACH_MSP7120_GW 4 /* PMC-Sierra MSP7120 Residential GW */
#define MACH_MSP7120_FPGA 5 /* PMC-Sierra MSP7120 Emulation */
#define MACH_MSP_OTHER 255 /* PMC-Sierra unknown board type */
#define CL_SIZE COMMAND_LINE_SIZE
const char *get_system_type(void);
......
......@@ -109,6 +109,7 @@
* Definitions for 7:0 on legacy processors
*/
#define PRID_REV_MASK 0x00ff
#define PRID_REV_TX4927 0x0022
#define PRID_REV_TX4937 0x0030
......@@ -125,6 +126,7 @@
#define PRID_REV_VR4122 0x0070
#define PRID_REV_VR4181A 0x0070 /* Same as VR4122 */
#define PRID_REV_VR4130 0x0080
#define PRID_REV_34K_V1_0_2 0x0022
/*
* Older processors used to encode processor version and revision in two
......
......@@ -15,6 +15,7 @@
#include <linux/linkage.h>
#include <asm/hazards.h>
#include <asm/war.h>
/*
* The following macros are especially useful for __asm__
......@@ -537,6 +538,9 @@
#define MIPS_CONF7_WII (_ULCAST_(1) << 31)
#define MIPS_CONF7_RPS (_ULCAST_(1) << 2)
/*
* Bits in the MIPS32/64 coprocessor 1 (FPU) revision register.
*/
......@@ -1298,10 +1302,39 @@ static inline void tlb_probe(void)
static inline void tlb_read(void)
{
#if MIPS34K_MISSED_ITLB_WAR
int res = 0;
__asm__ __volatile__(
" .set push \n"
" .set noreorder \n"
" .set noat \n"
" .set mips32r2 \n"
" .word 0x41610001 # dvpe $1 \n"
" move %0, $1 \n"
" ehb \n"
" .set pop \n"
: "=r" (res));
instruction_hazard();
#endif
__asm__ __volatile__(
".set noreorder\n\t"
"tlbr\n\t"
".set reorder");
#if MIPS34K_MISSED_ITLB_WAR
if ((res & _ULCAST_(1)))
__asm__ __volatile__(
" .set push \n"
" .set noreorder \n"
" .set noat \n"
" .set mips32r2 \n"
" .word 0x41600021 # evpe \n"
" ehb \n"
" .set pop \n");
#endif
}
static inline void tlb_write_indexed(void)
......
......@@ -197,6 +197,14 @@
#define R10000_LLSC_WAR 1
#endif
/*
* 34K core erratum: "Problems Executing the TLBR Instruction"
*/
#if defined(CONFIG_PMC_MSP7120_EVAL) || defined(CONFIG_PMC_MSP7120_GW) || \
defined(CONFIG_PMC_MSP7120_FPGA)
#define MIPS34K_MISSED_ITLB_WAR 1
#endif
/*
* Workarounds default to off
*/
......@@ -236,5 +244,8 @@
#ifndef R10000_LLSC_WAR
#define R10000_LLSC_WAR 0
#endif
#ifndef MIPS34K_MISSED_ITLB_WAR
#define MIPS34K_MISSED_ITLB_WAR 0
#endif
#endif /* _ASM_WAR_H */
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