[IA64] 4-level page tables
This patch introduces 4-level page tables to ia64. I have run some benchmarks and found nothing interesting. Performance has consistently fallen within the noise range. It also introduces a config option (setting the default to 3 levels). The config option prevents having 4 level page tables with 64k base page size. Signed-off-by:Robin Holt <holt@sgi.com> Signed-off-by:
Tony Luck <tony.luck@intel.com>
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- arch/ia64/Kconfig 13 additions, 0 deletionsarch/ia64/Kconfig
- arch/ia64/configs/sn2_defconfig 2 additions, 0 deletionsarch/ia64/configs/sn2_defconfig
- arch/ia64/defconfig 2 additions, 0 deletionsarch/ia64/defconfig
- arch/ia64/kernel/ivt.S 48 additions, 15 deletionsarch/ia64/kernel/ivt.S
- include/asm-ia64/page.h 6 additions, 2 deletionsinclude/asm-ia64/page.h
- include/asm-ia64/pgalloc.h 19 additions, 0 deletionsinclude/asm-ia64/pgalloc.h
- include/asm-ia64/pgtable.h 60 additions, 16 deletionsinclude/asm-ia64/pgtable.h
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