Commit 6eae43c5 authored by Gabor Juhos's avatar Gabor Juhos Committed by Ralf Baechle

MIPS: ath79: add GPIOLIB support

This patch implements generic GPIO routines for the built-in
GPIO controllers of the Atheros AR71XX/AR724X/AR913X SoCs.
Signed-off-by: default avatarGabor Juhos <juhosg@openwrt.org>
Signed-off-by: default avatarImre Kaloz <kaloz@openwrt.org>
Cc: David Brownell <dbrownell@users.sourceforge.net>
Cc: linux-mips@linux-mips.org
Cc: Luis R. Rodriguez <lrodriguez@atheros.com>
Cc: Cliff Holden <Cliff.Holden@Atheros.com>
Cc: Kathy Giori <Kathy.Giori@Atheros.com>
Patchwork: https://patchwork.linux-mips.org/patch/1948/Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent d4a67d9d
...@@ -68,6 +68,7 @@ config AR7 ...@@ -68,6 +68,7 @@ config AR7
config ATH79 config ATH79
bool "Atheros AR71XX/AR724X/AR913X based boards" bool "Atheros AR71XX/AR724X/AR913X based boards"
select ARCH_REQUIRE_GPIOLIB
select BOOT_RAW select BOOT_RAW
select CEVT_R4K select CEVT_R4K
select CSRC_R4K select CSRC_R4K
......
...@@ -8,7 +8,7 @@ ...@@ -8,7 +8,7 @@
# under the terms of the GNU General Public License version 2 as published # under the terms of the GNU General Public License version 2 as published
# by the Free Software Foundation. # by the Free Software Foundation.
obj-y := prom.o setup.o irq.o common.o clock.o obj-y := prom.o setup.o irq.o common.o clock.o gpio.o
obj-$(CONFIG_EARLY_PRINTK) += early_printk.o obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
......
...@@ -23,4 +23,9 @@ ...@@ -23,4 +23,9 @@
void ath79_clocks_init(void); void ath79_clocks_init(void);
void ath79_ddr_wb_flush(unsigned int reg); void ath79_ddr_wb_flush(unsigned int reg);
void ath79_gpio_function_enable(u32 mask);
void ath79_gpio_function_disable(u32 mask);
void ath79_gpio_function_setup(u32 set, u32 clear);
void ath79_gpio_init(void);
#endif /* __ATH79_COMMON_H */ #endif /* __ATH79_COMMON_H */
/*
* Atheros AR71XX/AR724X/AR913X GPIO API support
*
* Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
* Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published
* by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/module.h>
#include <linux/types.h>
#include <linux/spinlock.h>
#include <linux/io.h>
#include <linux/ioport.h>
#include <linux/gpio.h>
#include <asm/mach-ath79/ar71xx_regs.h>
#include <asm/mach-ath79/ath79.h>
#include "common.h"
static void __iomem *ath79_gpio_base;
static unsigned long ath79_gpio_count;
static DEFINE_SPINLOCK(ath79_gpio_lock);
static void __ath79_gpio_set_value(unsigned gpio, int value)
{
void __iomem *base = ath79_gpio_base;
if (value)
__raw_writel(1 << gpio, base + AR71XX_GPIO_REG_SET);
else
__raw_writel(1 << gpio, base + AR71XX_GPIO_REG_CLEAR);
}
static int __ath79_gpio_get_value(unsigned gpio)
{
return (__raw_readl(ath79_gpio_base + AR71XX_GPIO_REG_IN) >> gpio) & 1;
}
static int ath79_gpio_get_value(struct gpio_chip *chip, unsigned offset)
{
return __ath79_gpio_get_value(offset);
}
static void ath79_gpio_set_value(struct gpio_chip *chip,
unsigned offset, int value)
{
__ath79_gpio_set_value(offset, value);
}
static int ath79_gpio_direction_input(struct gpio_chip *chip,
unsigned offset)
{
void __iomem *base = ath79_gpio_base;
unsigned long flags;
spin_lock_irqsave(&ath79_gpio_lock, flags);
__raw_writel(__raw_readl(base + AR71XX_GPIO_REG_OE) & ~(1 << offset),
base + AR71XX_GPIO_REG_OE);
spin_unlock_irqrestore(&ath79_gpio_lock, flags);
return 0;
}
static int ath79_gpio_direction_output(struct gpio_chip *chip,
unsigned offset, int value)
{
void __iomem *base = ath79_gpio_base;
unsigned long flags;
spin_lock_irqsave(&ath79_gpio_lock, flags);
if (value)
__raw_writel(1 << offset, base + AR71XX_GPIO_REG_SET);
else
__raw_writel(1 << offset, base + AR71XX_GPIO_REG_CLEAR);
__raw_writel(__raw_readl(base + AR71XX_GPIO_REG_OE) | (1 << offset),
base + AR71XX_GPIO_REG_OE);
spin_unlock_irqrestore(&ath79_gpio_lock, flags);
return 0;
}
static struct gpio_chip ath79_gpio_chip = {
.label = "ath79",
.get = ath79_gpio_get_value,
.set = ath79_gpio_set_value,
.direction_input = ath79_gpio_direction_input,
.direction_output = ath79_gpio_direction_output,
.base = 0,
};
void ath79_gpio_function_enable(u32 mask)
{
void __iomem *base = ath79_gpio_base;
unsigned long flags;
spin_lock_irqsave(&ath79_gpio_lock, flags);
__raw_writel(__raw_readl(base + AR71XX_GPIO_REG_FUNC) | mask,
base + AR71XX_GPIO_REG_FUNC);
/* flush write */
__raw_readl(base + AR71XX_GPIO_REG_FUNC);
spin_unlock_irqrestore(&ath79_gpio_lock, flags);
}
void ath79_gpio_function_disable(u32 mask)
{
void __iomem *base = ath79_gpio_base;
unsigned long flags;
spin_lock_irqsave(&ath79_gpio_lock, flags);
__raw_writel(__raw_readl(base + AR71XX_GPIO_REG_FUNC) & ~mask,
base + AR71XX_GPIO_REG_FUNC);
/* flush write */
__raw_readl(base + AR71XX_GPIO_REG_FUNC);
spin_unlock_irqrestore(&ath79_gpio_lock, flags);
}
void ath79_gpio_function_setup(u32 set, u32 clear)
{
void __iomem *base = ath79_gpio_base;
unsigned long flags;
spin_lock_irqsave(&ath79_gpio_lock, flags);
__raw_writel((__raw_readl(base + AR71XX_GPIO_REG_FUNC) & ~clear) | set,
base + AR71XX_GPIO_REG_FUNC);
/* flush write */
__raw_readl(base + AR71XX_GPIO_REG_FUNC);
spin_unlock_irqrestore(&ath79_gpio_lock, flags);
}
void __init ath79_gpio_init(void)
{
int err;
if (soc_is_ar71xx())
ath79_gpio_count = AR71XX_GPIO_COUNT;
else if (soc_is_ar724x())
ath79_gpio_count = AR724X_GPIO_COUNT;
else if (soc_is_ar913x())
ath79_gpio_count = AR913X_GPIO_COUNT;
else
BUG();
ath79_gpio_base = ioremap_nocache(AR71XX_GPIO_BASE, AR71XX_GPIO_SIZE);
ath79_gpio_chip.ngpio = ath79_gpio_count;
err = gpiochip_add(&ath79_gpio_chip);
if (err)
panic("cannot add AR71xx GPIO chip, error=%d", err);
}
int gpio_get_value(unsigned gpio)
{
if (gpio < ath79_gpio_count)
return __ath79_gpio_get_value(gpio);
return __gpio_get_value(gpio);
}
EXPORT_SYMBOL(gpio_get_value);
void gpio_set_value(unsigned gpio, int value)
{
if (gpio < ath79_gpio_count)
__ath79_gpio_set_value(gpio, value);
else
__gpio_set_value(gpio, value);
}
EXPORT_SYMBOL(gpio_set_value);
int gpio_to_irq(unsigned gpio)
{
/* FIXME */
return -EINVAL;
}
EXPORT_SYMBOL(gpio_to_irq);
int irq_to_gpio(unsigned irq)
{
/* FIXME */
return -EINVAL;
}
EXPORT_SYMBOL(irq_to_gpio);
...@@ -157,7 +157,6 @@ void __init plat_mem_setup(void) ...@@ -157,7 +157,6 @@ void __init plat_mem_setup(void)
AR71XX_RESET_SIZE); AR71XX_RESET_SIZE);
ath79_pll_base = ioremap_nocache(AR71XX_PLL_BASE, ath79_pll_base = ioremap_nocache(AR71XX_PLL_BASE,
AR71XX_PLL_SIZE); AR71XX_PLL_SIZE);
ath79_ddr_base = ioremap_nocache(AR71XX_DDR_CTRL_BASE, ath79_ddr_base = ioremap_nocache(AR71XX_DDR_CTRL_BASE,
AR71XX_DDR_CTRL_SIZE); AR71XX_DDR_CTRL_SIZE);
...@@ -183,6 +182,7 @@ void __init plat_time_init(void) ...@@ -183,6 +182,7 @@ void __init plat_time_init(void)
static int __init ath79_setup(void) static int __init ath79_setup(void)
{ {
ath79_gpio_init();
ath79_register_uart(); ath79_register_uart();
return 0; return 0;
} }
......
...@@ -25,6 +25,8 @@ ...@@ -25,6 +25,8 @@
#define AR71XX_DDR_CTRL_SIZE 0x100 #define AR71XX_DDR_CTRL_SIZE 0x100
#define AR71XX_UART_BASE (AR71XX_APB_BASE + 0x00020000) #define AR71XX_UART_BASE (AR71XX_APB_BASE + 0x00020000)
#define AR71XX_UART_SIZE 0x100 #define AR71XX_UART_SIZE 0x100
#define AR71XX_GPIO_BASE (AR71XX_APB_BASE + 0x00040000)
#define AR71XX_GPIO_SIZE 0x100
#define AR71XX_PLL_BASE (AR71XX_APB_BASE + 0x00050000) #define AR71XX_PLL_BASE (AR71XX_APB_BASE + 0x00050000)
#define AR71XX_PLL_SIZE 0x100 #define AR71XX_PLL_SIZE 0x100
#define AR71XX_RESET_BASE (AR71XX_APB_BASE + 0x00060000) #define AR71XX_RESET_BASE (AR71XX_APB_BASE + 0x00060000)
...@@ -204,4 +206,23 @@ ...@@ -204,4 +206,23 @@
#define AR71XX_SPI_IOC_CS_ALL (AR71XX_SPI_IOC_CS0 | AR71XX_SPI_IOC_CS1 | \ #define AR71XX_SPI_IOC_CS_ALL (AR71XX_SPI_IOC_CS0 | AR71XX_SPI_IOC_CS1 | \
AR71XX_SPI_IOC_CS2) AR71XX_SPI_IOC_CS2)
/*
* GPIO block
*/
#define AR71XX_GPIO_REG_OE 0x00
#define AR71XX_GPIO_REG_IN 0x04
#define AR71XX_GPIO_REG_OUT 0x08
#define AR71XX_GPIO_REG_SET 0x0c
#define AR71XX_GPIO_REG_CLEAR 0x10
#define AR71XX_GPIO_REG_INT_MODE 0x14
#define AR71XX_GPIO_REG_INT_TYPE 0x18
#define AR71XX_GPIO_REG_INT_POLARITY 0x1c
#define AR71XX_GPIO_REG_INT_PENDING 0x20
#define AR71XX_GPIO_REG_INT_ENABLE 0x24
#define AR71XX_GPIO_REG_FUNC 0x28
#define AR71XX_GPIO_COUNT 16
#define AR724X_GPIO_COUNT 18
#define AR913X_GPIO_COUNT 22
#endif /* __ASM_MACH_AR71XX_REGS_H */ #endif /* __ASM_MACH_AR71XX_REGS_H */
/*
* Atheros AR71XX/AR724X/AR913X GPIO API definitions
*
* Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
* Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published
* by the Free Software Foundation.
*
*/
#ifndef __ASM_MACH_ATH79_GPIO_H
#define __ASM_MACH_ATH79_GPIO_H
#define ARCH_NR_GPIOS 64
#include <asm-generic/gpio.h>
int gpio_to_irq(unsigned gpio);
int irq_to_gpio(unsigned irq);
int gpio_get_value(unsigned gpio);
void gpio_set_value(unsigned gpio, int value);
#define gpio_cansleep __gpio_cansleep
#endif /* __ASM_MACH_ATH79_GPIO_H */
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