Commit 4565f017 authored by FUJITA Tomonori's avatar FUJITA Tomonori Committed by Linus Torvalds

dma-mapping: unify dma_get_cache_alignment implementations

dma_get_cache_alignment returns the minimum DMA alignment.  Architectures
defines it as ARCH_DMA_MINALIGN (formally ARCH_KMALLOC_MINALIGN).  So we
can unify dma_get_cache_alignment implementations.

Note that some architectures implement dma_get_cache_alignment wrongly.
dma_get_cache_alignment() should return the minimum DMA alignment.  So
fully-coherent architectures should return 1.  This patch also fixes this
issue.
Signed-off-by: default avatarFUJITA Tomonori <fujita.tomonori@lab.ntt.co.jp>
Cc: <linux-arch@vger.kernel.org>
Signed-off-by: default avatarAndrew Morton <akpm@linux-foundation.org>
Signed-off-by: default avatarLinus Torvalds <torvalds@linux-foundation.org>
parent a6eb9fe1
......@@ -44,6 +44,5 @@ static inline int dma_set_mask(struct device *dev, u64 mask)
#define dma_is_consistent(d, h) (1)
#define dma_cache_sync(dev, va, size, dir) ((void)0)
#define dma_get_cache_alignment() L1_CACHE_BYTES
#endif /* _ALPHA_DMA_MAPPING_H */
......@@ -144,11 +144,6 @@ static inline int dma_set_mask(struct device *dev, u64 dma_mask)
return 0;
}
static inline int dma_get_cache_alignment(void)
{
return 32;
}
static inline int dma_is_consistent(struct device *dev, dma_addr_t handle)
{
return !!arch_is_coherent();
......
......@@ -341,9 +341,4 @@ static inline int dma_is_consistent(struct device *dev, dma_addr_t dma_addr)
return 1;
}
static inline int dma_get_cache_alignment(void)
{
return boot_cpu_data.dcache.linesz;
}
#endif /* __ASM_AVR32_DMA_MAPPING_H */
......@@ -21,7 +21,6 @@ void dma_free_coherent(struct device *dev, size_t size, void *vaddr,
#define dma_alloc_noncoherent(d, s, h, f) dma_alloc_coherent(d, s, h, f)
#define dma_free_noncoherent(d, s, v, h) dma_free_coherent(d, s, v, h)
#define dma_supported(d, m) (1)
#define dma_get_cache_alignment() (32)
#define dma_is_consistent(d, h) (1)
static inline int
......
......@@ -152,12 +152,6 @@ dma_set_mask(struct device *dev, u64 mask)
return 0;
}
static inline int
dma_get_cache_alignment(void)
{
return (1 << INTERNODE_CACHE_SHIFT);
}
#define dma_is_consistent(d, h) (1)
static inline void
......
......@@ -125,12 +125,6 @@ int dma_set_mask(struct device *dev, u64 mask)
return 0;
}
static inline
int dma_get_cache_alignment(void)
{
return 1 << L1_CACHE_SHIFT;
}
#define dma_is_consistent(d, h) (1)
static inline
......
......@@ -86,8 +86,6 @@ static inline phys_addr_t dma_to_phys(struct device *dev, dma_addr_t daddr)
return daddr;
}
extern int dma_get_cache_alignment(void);
static inline void
dma_cache_sync (struct device *dev, void *vaddr, size_t size,
enum dma_data_direction dir)
......
......@@ -98,12 +98,6 @@ static struct resource bss_resource = {
unsigned long ia64_max_cacheline_size;
int dma_get_cache_alignment(void)
{
return ia64_max_cacheline_size;
}
EXPORT_SYMBOL(dma_get_cache_alignment);
unsigned long ia64_iobase; /* virtual address for I/O accesses */
EXPORT_SYMBOL(ia64_iobase);
struct io_space io_space[MAX_IO_SPACES];
......
......@@ -16,11 +16,6 @@ static inline int dma_set_mask(struct device *dev, u64 mask)
return 0;
}
static inline int dma_get_cache_alignment(void)
{
return 1 << L1_CACHE_SHIFT;
}
static inline int dma_is_consistent(struct device *dev, dma_addr_t dma_addr)
{
return 0;
......
......@@ -132,11 +132,6 @@ static inline void dma_free_coherent(struct device *dev, size_t size,
ops->free_coherent(dev, size, cpu_addr, dma_handle);
}
static inline int dma_get_cache_alignment(void)
{
return L1_CACHE_BYTES;
}
static inline void dma_cache_sync(struct device *dev, void *vaddr, size_t size,
enum dma_data_direction direction)
{
......
......@@ -62,13 +62,6 @@ dma_set_mask(struct device *dev, u64 mask)
return 0;
}
static inline int
dma_get_cache_alignment(void)
{
/* XXX Largest on any MIPS */
return 128;
}
extern int dma_is_consistent(struct device *dev, dma_addr_t dma_addr);
extern void dma_cache_sync(struct device *dev, void *vaddr, size_t size,
......
......@@ -161,12 +161,6 @@ int dma_set_mask(struct device *dev, u64 mask)
return 0;
}
static inline
int dma_get_cache_alignment(void)
{
return 1 << L1_CACHE_SHIFT;
}
#define dma_is_consistent(d) (1)
static inline
......
......@@ -184,12 +184,6 @@ dma_set_mask(struct device *dev, u64 mask)
return 0;
}
static inline int
dma_get_cache_alignment(void)
{
return dcache_stride;
}
static inline int
dma_is_consistent(struct device *dev, dma_addr_t dma_addr)
{
......
......@@ -215,21 +215,6 @@ static inline phys_addr_t dma_to_phys(struct device *dev, dma_addr_t daddr)
#define dma_is_consistent(d, h) (1)
#endif
static inline int dma_get_cache_alignment(void)
{
#ifdef CONFIG_PPC64
/* no easy way to get cache size on all processors, so return
* the maximum possible, to be safe */
return (1 << INTERNODE_CACHE_SHIFT);
#else
/*
* Each processor family will define its own L1_CACHE_SHIFT,
* L1_CACHE_BYTES wraps to this, so this is always safe.
*/
return L1_CACHE_BYTES;
#endif
}
static inline void dma_cache_sync(struct device *dev, void *vaddr, size_t size,
enum dma_data_direction direction)
{
......
......@@ -48,15 +48,6 @@ void dma_cache_sync(struct device *dev, void *vaddr, size_t size,
#define dma_is_consistent(d, h) (0)
#endif
static inline int dma_get_cache_alignment(void)
{
/*
* Each processor family will define its own L1_CACHE_SHIFT,
* L1_CACHE_BYTES wraps to this, so this is always safe.
*/
return L1_CACHE_BYTES;
}
static inline int dma_mapping_error(struct device *dev, dma_addr_t dma_addr)
{
struct dma_map_ops *ops = get_dma_ops(dev);
......
......@@ -52,15 +52,6 @@ static inline int dma_mapping_error(struct device *dev, dma_addr_t dma_addr)
return (dma_addr == DMA_ERROR_CODE);
}
static inline int dma_get_cache_alignment(void)
{
/*
* no easy way to get cache size on all processors, so return
* the maximum possible, to be safe
*/
return (1 << INTERNODE_CACHE_SHIFT);
}
static inline int dma_set_mask(struct device *dev, u64 mask)
{
#ifdef CONFIG_PCI
......
......@@ -90,13 +90,6 @@ dma_set_mask(struct device *dev, u64 mask)
return 0;
}
static inline int
dma_get_cache_alignment(void)
{
return L2_CACHE_BYTES;
}
#define dma_is_consistent(d, h) (1)
#endif /* _ASM_TILE_DMA_MAPPING_H */
......@@ -87,13 +87,6 @@ dma_cache_sync(struct device *dev, void *vaddr, size_t size,
flush_write_buffers();
}
static inline int dma_get_cache_alignment(void)
{
/* no easy way to get cache size on all x86, so return the
* maximum possible, to be safe */
return boot_cpu_data.x86_clflush_size;
}
static inline unsigned long dma_alloc_coherent_mask(struct device *dev,
gfp_t gfp)
{
......
......@@ -161,12 +161,6 @@ dma_set_mask(struct device *dev, u64 mask)
return 0;
}
static inline int
dma_get_cache_alignment(void)
{
return L1_CACHE_BYTES;
}
#define dma_is_consistent(d, h) (1)
static inline void
......
......@@ -142,6 +142,14 @@ static inline int dma_set_seg_boundary(struct device *dev, unsigned long mask)
return -EIO;
}
static inline int dma_get_cache_alignment(void)
{
#ifdef ARCH_DMA_MINALIGN
return ARCH_DMA_MINALIGN;
#endif
return 1;
}
/* flags for the coherent memory api */
#define DMA_MEMORY_MAP 0x01
#define DMA_MEMORY_IO 0x02
......
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