Commit 44eeab67 authored by Ralf Baechle's avatar Ralf Baechle
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MIPS: Hibernation: Remove SMP TLB and cacheflushing code.

We can't perform any flushes on SMP from swsusp_arch_resume because
interrupts are disabled.  A cross-CPU flush is unnecessary anyway
because all but the local CPU have already been disabled.  A local
flush is not needed either because we didn't change any mappings.  So
just delete the code.
Signed-off-by: default avatarRalf Baechle <>
parent 631330f5
......@@ -43,15 +43,6 @@ LEAF(swsusp_arch_resume)
bne t1, t3, 1b
PTR_L t0, PBE_NEXT(t0)
bnez t0, 0b
/* flush caches to make sure context is in memory */
PTR_L t0, __flush_cache_all
jalr t0
/* flush tlb entries */
jal flush_tlb_all
jal local_flush_tlb_all
PTR_LA t0, saved_regs
PTR_L ra, PT_R31(t0)
PTR_L sp, PT_R29(t0)
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