Commit 42a3b4f2 authored by Ralf Baechle's avatar Ralf Baechle Committed by Linus Torvalds

[PATCH] mips: nuke trailing whitespace

Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
Signed-off-by: default avatarAndrew Morton <akpm@osdl.org>
Signed-off-by: default avatarLinus Torvalds <torvalds@osdl.org>
parent 875d43e7
...@@ -177,7 +177,7 @@ cflags-$(CONFIG_CPU_MIPS64) += \ ...@@ -177,7 +177,7 @@ cflags-$(CONFIG_CPU_MIPS64) += \
cflags-$(CONFIG_CPU_R5000) += \ cflags-$(CONFIG_CPU_R5000) += \
$(call set_gccflags,r5000,mips4,r5000,mips4,mips2) \ $(call set_gccflags,r5000,mips4,r5000,mips4,mips2) \
-Wa,--trap -Wa,--trap
cflags-$(CONFIG_CPU_R5432) += \ cflags-$(CONFIG_CPU_R5432) += \
$(call set_gccflags,r5400,mips4,r5000,mips4,mips2) \ $(call set_gccflags,r5400,mips4,r5000,mips4,mips2) \
...@@ -720,7 +720,7 @@ archclean: ...@@ -720,7 +720,7 @@ archclean:
@$(MAKE) $(clean)=arch/mips/boot @$(MAKE) $(clean)=arch/mips/boot
@$(MAKE) $(clean)=arch/mips/lasat @$(MAKE) $(clean)=arch/mips/lasat
# Generate <asm/offset.h # Generate <asm/offset.h
# #
# The default rule is suffering from funny problems on MIPS so we using our # The default rule is suffering from funny problems on MIPS so we using our
# own ... # own ...
......
...@@ -40,14 +40,14 @@ ...@@ -40,14 +40,14 @@
/* TBD */ /* TBD */
static struct resource pci_io_resource = { static struct resource pci_io_resource = {
"pci IO space", "pci IO space",
(u32)PCI_IO_START, (u32)PCI_IO_START,
(u32)PCI_IO_END, (u32)PCI_IO_END,
IORESOURCE_IO IORESOURCE_IO
}; };
static struct resource pci_mem_resource = { static struct resource pci_mem_resource = {
"pci memory space", "pci memory space",
(u32)PCI_MEM_START, (u32)PCI_MEM_START,
(u32)PCI_MEM_END, (u32)PCI_MEM_END,
IORESOURCE_MEM IORESOURCE_MEM
...@@ -68,7 +68,7 @@ static unsigned long virt_io_addr; ...@@ -68,7 +68,7 @@ static unsigned long virt_io_addr;
static int __init au1x_pci_setup(void) static int __init au1x_pci_setup(void)
{ {
#if defined(CONFIG_SOC_AU1500) || defined(CONFIG_SOC_AU1550) #if defined(CONFIG_SOC_AU1500) || defined(CONFIG_SOC_AU1550)
virt_io_addr = (unsigned long)ioremap(Au1500_PCI_IO_START, virt_io_addr = (unsigned long)ioremap(Au1500_PCI_IO_START,
Au1500_PCI_IO_END - Au1500_PCI_IO_START + 1); Au1500_PCI_IO_END - Au1500_PCI_IO_START + 1);
if (!virt_io_addr) { if (!virt_io_addr) {
...@@ -77,7 +77,7 @@ static int __init au1x_pci_setup(void) ...@@ -77,7 +77,7 @@ static int __init au1x_pci_setup(void)
} }
#ifdef CONFIG_DMA_NONCOHERENT #ifdef CONFIG_DMA_NONCOHERENT
/* /*
* Set the NC bit in controller for Au1500 pre-AC silicon * Set the NC bit in controller for Au1500 pre-AC silicon
*/ */
u32 prid = read_c0_prid(); u32 prid = read_c0_prid();
......
...@@ -97,7 +97,7 @@ static int __init au1x00_setup(void) ...@@ -97,7 +97,7 @@ static int __init au1x00_setup(void)
argptr = prom_getcmdline(); argptr = prom_getcmdline();
strcat(argptr, " console=ttyS0,115200"); strcat(argptr, " console=ttyS0,115200");
} }
#endif #endif
#ifdef CONFIG_FB_AU1100 #ifdef CONFIG_FB_AU1100
if ((argptr = strstr(argptr, "video=")) == NULL) { if ((argptr = strstr(argptr, "video=")) == NULL) {
......
...@@ -281,7 +281,7 @@ unsigned long cal_r4koff(void) ...@@ -281,7 +281,7 @@ unsigned long cal_r4koff(void)
cpu_speed = count * 2; cpu_speed = count * 2;
} }
#else #else
cpu_speed = (au_readl(SYS_CPUPLL) & 0x0000003f) * cpu_speed = (au_readl(SYS_CPUPLL) & 0x0000003f) *
AU1000_SRC_CLK; AU1000_SRC_CLK;
count = cpu_speed / 2; count = cpu_speed / 2;
#endif #endif
...@@ -356,7 +356,7 @@ static unsigned long do_fast_cp0_gettimeoffset(void) ...@@ -356,7 +356,7 @@ static unsigned long do_fast_cp0_gettimeoffset(void)
: "hi", "lo", GCC_REG_ACCUM); : "hi", "lo", GCC_REG_ACCUM);
/* /*
* Due to possible jiffies inconsistencies, we need to check * Due to possible jiffies inconsistencies, we need to check
* the result so that we'll get a timer that is monotonic. * the result so that we'll get a timer that is monotonic.
*/ */
if (res >= USECS_PER_JIFFY) if (res >= USECS_PER_JIFFY)
...@@ -375,8 +375,8 @@ static unsigned long do_fast_pm_gettimeoffset(void) ...@@ -375,8 +375,8 @@ static unsigned long do_fast_pm_gettimeoffset(void)
au_sync(); au_sync();
offset = pc0 - last_pc0; offset = pc0 - last_pc0;
if (offset > 2*MATCH20_INC) { if (offset > 2*MATCH20_INC) {
printk("huge offset %x, last_pc0 %x last_match20 %x pc0 %x\n", printk("huge offset %x, last_pc0 %x last_match20 %x pc0 %x\n",
(unsigned)offset, (unsigned)last_pc0, (unsigned)offset, (unsigned)last_pc0,
(unsigned)last_match20, (unsigned)pc0); (unsigned)last_match20, (unsigned)pc0);
} }
offset = (unsigned long)((offset * 305) / 10); offset = (unsigned long)((offset * 305) / 10);
...@@ -394,11 +394,11 @@ void au1xxx_timer_setup(struct irqaction *irq) ...@@ -394,11 +394,11 @@ void au1xxx_timer_setup(struct irqaction *irq)
r4k_offset = cal_r4koff(); r4k_offset = cal_r4koff();
printk("%08lx(%d)\n", r4k_offset, (int) r4k_offset); printk("%08lx(%d)\n", r4k_offset, (int) r4k_offset);
//est_freq = 2*r4k_offset*HZ; //est_freq = 2*r4k_offset*HZ;
est_freq = r4k_offset*HZ; est_freq = r4k_offset*HZ;
est_freq += 5000; /* round */ est_freq += 5000; /* round */
est_freq -= est_freq%10000; est_freq -= est_freq%10000;
printk("CPU frequency %d.%02d MHz\n", est_freq/1000000, printk("CPU frequency %d.%02d MHz\n", est_freq/1000000,
(est_freq%1000000)*100/1000000); (est_freq%1000000)*100/1000000);
set_au1x00_speed(est_freq); set_au1x00_speed(est_freq);
set_au1x00_lcd_clock(); // program the LCD clock set_au1x00_lcd_clock(); // program the LCD clock
......
...@@ -182,7 +182,7 @@ void __init board_setup(void) ...@@ -182,7 +182,7 @@ void __init board_setup(void)
au_writel(0xf0000000, Au1500_PCI_MWMASK_DEV); au_writel(0xf0000000, Au1500_PCI_MWMASK_DEV);
au_writel(0, Au1500_PCI_MWBASE_REV_CCL); au_writel(0, Au1500_PCI_MWBASE_REV_CCL);
au_writel(0x02a00356, Au1500_PCI_STATCMD); au_writel(0x02a00356, Au1500_PCI_STATCMD);
au_writel(0x00003c04, Au1500_PCI_HDRTYPE); au_writel(0x00003c04, Au1500_PCI_HDRTYPE);
au_writel(0x00000008, Au1500_PCI_MBAR); au_writel(0x00000008, Au1500_PCI_MBAR);
au_sync(); au_sync();
...@@ -216,7 +216,7 @@ csb250_pci_idsel(unsigned int devsel, int assert) ...@@ -216,7 +216,7 @@ csb250_pci_idsel(unsigned int devsel, int assert)
unsigned int gpio2_pins; unsigned int gpio2_pins;
retval = 1; retval = 1;
/* First, disable both selects, then assert the one requested. /* First, disable both selects, then assert the one requested.
*/ */
au_writel(0xc000c000, GPIO2_OUTPUT); au_writel(0xc000c000, GPIO2_OUTPUT);
......
...@@ -81,7 +81,7 @@ int __init prom_init(int argc, char **argv, char **envp, int *prom_vec) ...@@ -81,7 +81,7 @@ int __init prom_init(int argc, char **argv, char **envp, int *prom_vec)
csb_env[0] = env1; csb_env[0] = env1;
mips_machgroup = MACH_GROUP_ALCHEMY; mips_machgroup = MACH_GROUP_ALCHEMY;
mips_machtype = MACH_CSB250; mips_machtype = MACH_CSB250;
prom_init_cmdline(); prom_init_cmdline();
memsize_str = prom_getenv("memsize"); memsize_str = prom_getenv("memsize");
......
...@@ -61,7 +61,7 @@ void __init prom_init(void) ...@@ -61,7 +61,7 @@ void __init prom_init(void)
prom_envp = (char **) fw_arg2; prom_envp = (char **) fw_arg2;
mips_machgroup = MACH_GROUP_ALCHEMY; mips_machgroup = MACH_GROUP_ALCHEMY;
mips_machtype = MACH_DB1000; /* set the platform # */ mips_machtype = MACH_DB1000; /* set the platform # */
prom_init_cmdline(); prom_init_cmdline();
......
...@@ -63,7 +63,7 @@ int __init prom_init(int argc, char **argv, char **envp, int *prom_vec) ...@@ -63,7 +63,7 @@ int __init prom_init(int argc, char **argv, char **envp, int *prom_vec)
prom_envp = envp; prom_envp = envp;
mips_machgroup = MACH_GROUP_ALCHEMY; mips_machgroup = MACH_GROUP_ALCHEMY;
mips_machtype = MACH_DB1000; /* set the platform # */ mips_machtype = MACH_DB1000; /* set the platform # */
prom_init_cmdline(); prom_init_cmdline();
memsize_str = prom_getenv("memsize"); memsize_str = prom_getenv("memsize");
......
...@@ -174,7 +174,7 @@ void __init board_setup(void) ...@@ -174,7 +174,7 @@ void __init board_setup(void)
case 0x02: /* HB */ case 0x02: /* HB */
break; break;
default: /* HC and newer */ default: /* HC and newer */
/* Enable sys bus clock divider when IDLE state or no bus /* Enable sys bus clock divider when IDLE state or no bus
activity. */ activity. */
au_writel(au_readl(SYS_POWERCTRL) | (0x3 << 5), SYS_POWERCTRL); au_writel(au_readl(SYS_POWERCTRL) | (0x3 << 5), SYS_POWERCTRL);
break; break;
......
...@@ -49,7 +49,7 @@ void board_reset (void) ...@@ -49,7 +49,7 @@ void board_reset (void)
void __init board_setup(void) void __init board_setup(void)
{ {
u32 pin_func; u32 pin_func;
// set multiple use pins (UART3/GPIO) to UART (it's used as UART too) // set multiple use pins (UART3/GPIO) to UART (it's used as UART too)
pin_func = au_readl(SYS_PINFUNC) & (u32)(~SYS_PF_UR3); pin_func = au_readl(SYS_PINFUNC) & (u32)(~SYS_PF_UR3);
pin_func |= SYS_PF_UR3; pin_func |= SYS_PF_UR3;
...@@ -75,11 +75,11 @@ void __init board_setup(void) ...@@ -75,11 +75,11 @@ void __init board_setup(void)
au_writel(1, GPIO2_ENABLE); au_writel(1, GPIO2_ENABLE);
/* gpio2 208/9/10/11 are inputs */ /* gpio2 208/9/10/11 are inputs */
au_writel((1<<8) | (1<<9) | (1<<10) | (1<<11), GPIO2_DIR); au_writel((1<<8) | (1<<9) | (1<<10) | (1<<11), GPIO2_DIR);
/* turn off power */ /* turn off power */
au_writel((au_readl(GPIO2_PINSTATE) & ~(1<<14))|(1<<30), GPIO2_OUTPUT); au_writel((au_readl(GPIO2_PINSTATE) & ~(1<<14))|(1<<30), GPIO2_OUTPUT);
#endif #endif
#ifdef CONFIG_PCI #ifdef CONFIG_PCI
#if defined(__MIPSEB__) #if defined(__MIPSEB__)
......
...@@ -55,7 +55,7 @@ void __init prom_init(void) ...@@ -55,7 +55,7 @@ void __init prom_init(void)
prom_envp = (char **) fw_arg2; prom_envp = (char **) fw_arg2;
mips_machgroup = MACH_GROUP_ALCHEMY; mips_machgroup = MACH_GROUP_ALCHEMY;
mips_machtype = MACH_XXS1500; /* set the platform # */ mips_machtype = MACH_XXS1500; /* set the platform # */
prom_init_cmdline(); prom_init_cmdline();
......
...@@ -56,7 +56,7 @@ au1xxx_irq_map_t au1xxx_irq_map[] = { ...@@ -56,7 +56,7 @@ au1xxx_irq_map_t au1xxx_irq_map[] = {
{ AU1500_GPIO_207, INTC_INT_LOW_LEVEL, 0 }, { AU1500_GPIO_207, INTC_INT_LOW_LEVEL, 0 },
{ AU1000_GPIO_0, INTC_INT_LOW_LEVEL, 0 }, { AU1000_GPIO_0, INTC_INT_LOW_LEVEL, 0 },
{ AU1000_GPIO_1, INTC_INT_LOW_LEVEL, 0 }, { AU1000_GPIO_1, INTC_INT_LOW_LEVEL, 0 },
{ AU1000_GPIO_2, INTC_INT_LOW_LEVEL, 0 }, { AU1000_GPIO_2, INTC_INT_LOW_LEVEL, 0 },
{ AU1000_GPIO_3, INTC_INT_LOW_LEVEL, 0 }, { AU1000_GPIO_3, INTC_INT_LOW_LEVEL, 0 },
{ AU1000_GPIO_4, INTC_INT_LOW_LEVEL, 0 }, /* CF interrupt */ { AU1000_GPIO_4, INTC_INT_LOW_LEVEL, 0 }, /* CF interrupt */
......
...@@ -76,7 +76,7 @@ set_pci_int_attr(u32 pci, u32 intn, u32 active, u32 trigger) ...@@ -76,7 +76,7 @@ set_pci_int_attr(u32 pci, u32 intn, u32 active, u32 trigger)
extern void vrc5477_irq_init(u32 base); extern void vrc5477_irq_init(u32 base);
extern void mips_cpu_irq_init(u32 base); extern void mips_cpu_irq_init(u32 base);
extern asmlinkage void ddb5477_handle_int(void); extern asmlinkage void ddb5477_handle_int(void);
extern int setup_irq(unsigned int irq, struct irqaction *irqaction); extern int setup_irq(unsigned int irq, struct irqaction *irqaction);
static struct irqaction irq_cascade = { no_action, 0, CPU_MASK_NONE, "cascade", NULL, NULL }; static struct irqaction irq_cascade = { no_action, 0, CPU_MASK_NONE, "cascade", NULL, NULL };
void __init arch_init_irq(void) void __init arch_init_irq(void)
...@@ -94,7 +94,7 @@ void __init arch_init_irq(void) ...@@ -94,7 +94,7 @@ void __init arch_init_irq(void)
/* setup PCI interrupt attributes */ /* setup PCI interrupt attributes */
set_pci_int_attr(PCI0, INTA, ACTIVE_LOW, LEVEL_SENSE); set_pci_int_attr(PCI0, INTA, ACTIVE_LOW, LEVEL_SENSE);
set_pci_int_attr(PCI0, INTB, ACTIVE_LOW, LEVEL_SENSE); set_pci_int_attr(PCI0, INTB, ACTIVE_LOW, LEVEL_SENSE);
if (mips_machtype == MACH_NEC_ROCKHOPPERII) if (mips_machtype == MACH_NEC_ROCKHOPPERII)
set_pci_int_attr(PCI0, INTC, ACTIVE_HIGH, LEVEL_SENSE); set_pci_int_attr(PCI0, INTC, ACTIVE_HIGH, LEVEL_SENSE);
else else
set_pci_int_attr(PCI0, INTC, ACTIVE_LOW, LEVEL_SENSE); set_pci_int_attr(PCI0, INTC, ACTIVE_LOW, LEVEL_SENSE);
...@@ -134,7 +134,7 @@ void __init arch_init_irq(void) ...@@ -134,7 +134,7 @@ void __init arch_init_irq(void)
/* setup cascade interrupts */ /* setup cascade interrupts */
setup_irq(VRC5477_IRQ_BASE + VRC5477_I8259_CASCADE, &irq_cascade); setup_irq(VRC5477_IRQ_BASE + VRC5477_I8259_CASCADE, &irq_cascade);
setup_irq(CPU_IRQ_BASE + CPU_VRC5477_CASCADE, &irq_cascade); setup_irq(CPU_IRQ_BASE + CPU_VRC5477_CASCADE, &irq_cascade);
/* hook up the first-level interrupt handler */ /* hook up the first-level interrupt handler */
set_except_vector(0, ddb5477_handle_int); set_except_vector(0, ddb5477_handle_int);
......
...@@ -141,7 +141,7 @@ static void __init ddb_time_init(void) ...@@ -141,7 +141,7 @@ static void __init ddb_time_init(void)
/* mips_hpt_frequency is 1/2 of the cpu core freq */ /* mips_hpt_frequency is 1/2 of the cpu core freq */
i = (read_c0_config() >> 28 ) & 7; i = (read_c0_config() >> 28 ) & 7;
if ((current_cpu_data.cputype == CPU_R5432) && (i == 3)) if ((current_cpu_data.cputype == CPU_R5432) && (i == 3))
i = 4; i = 4;
mips_hpt_frequency = bus_frequency*(i+4)/4; mips_hpt_frequency = bus_frequency*(i+4)/4;
} }
...@@ -298,11 +298,11 @@ static void __init ddb5477_board_init(void) ...@@ -298,11 +298,11 @@ static void __init ddb5477_board_init(void)
if (mips_machtype == MACH_NEC_ROCKHOPPER if (mips_machtype == MACH_NEC_ROCKHOPPER
|| mips_machtype == MACH_NEC_ROCKHOPPERII) { || mips_machtype == MACH_NEC_ROCKHOPPERII) {
/* Disable bus diagnostics. */ /* Disable bus diagnostics. */
ddb_out32(DDB_PCICTL0_L, 0); ddb_out32(DDB_PCICTL0_L, 0);
ddb_out32(DDB_PCICTL0_H, 0); ddb_out32(DDB_PCICTL0_H, 0);
ddb_out32(DDB_PCICTL1_L, 0); ddb_out32(DDB_PCICTL1_L, 0);
ddb_out32(DDB_PCICTL1_H, 0); ddb_out32(DDB_PCICTL1_H, 0);
} }
if (mips_machtype == MACH_NEC_ROCKHOPPER) { if (mips_machtype == MACH_NEC_ROCKHOPPER) {
...@@ -354,7 +354,7 @@ static void __init ddb5477_board_init(void) ...@@ -354,7 +354,7 @@ static void __init ddb5477_board_init(void)
*/ */
pci_write_config_byte(&dev_m1533, 0x58, 0x74); pci_write_config_byte(&dev_m1533, 0x58, 0x74);
/* /*
* positive decode (bit6 -0) * positive decode (bit6 -0)
* enable IDE controler interrupt (bit 4 -1) * enable IDE controler interrupt (bit 4 -1)
* setup SIRQ to point to IRQ 14 (bit 3:0 - 1101) * setup SIRQ to point to IRQ 14 (bit 3:0 - 1101)
...@@ -364,31 +364,31 @@ static void __init ddb5477_board_init(void) ...@@ -364,31 +364,31 @@ static void __init ddb5477_board_init(void)
/* Setup M5229 registers */ /* Setup M5229 registers */
dev_m5229.bus = &bus; dev_m5229.bus = &bus;
dev_m5229.sysdata = NULL; dev_m5229.sysdata = NULL;
dev_m5229.devfn = 4*8; // slot 4 (AD15): M5229 IDE dev_m5229.devfn = 4*8; // slot 4 (AD15): M5229 IDE
/* /*
* enable IDE in the M5229 config register 0x50 (bit 0 - 1) * enable IDE in the M5229 config register 0x50 (bit 0 - 1)
* M5229 IDSEL is addr:15; see above setting * M5229 IDSEL is addr:15; see above setting
*/ */
pci_read_config_byte(&dev_m5229, 0x50, &temp8); pci_read_config_byte(&dev_m5229, 0x50, &temp8);
pci_write_config_byte(&dev_m5229, 0x50, temp8 | 0x1); pci_write_config_byte(&dev_m5229, 0x50, temp8 | 0x1);
/* /*
* enable bus master (bit 2) and IO decoding (bit 0) * enable bus master (bit 2) and IO decoding (bit 0)
*/ */
pci_read_config_byte(&dev_m5229, 0x04, &temp8); pci_read_config_byte(&dev_m5229, 0x04, &temp8);
pci_write_config_byte(&dev_m5229, 0x04, temp8 | 0x5); pci_write_config_byte(&dev_m5229, 0x04, temp8 | 0x5);
/* /*
* enable native, copied from arch/ppc/k2boot/head.S * enable native, copied from arch/ppc/k2boot/head.S
* TODO - need volatile, need to be portable * TODO - need volatile, need to be portable
*/ */
pci_write_config_byte(&dev_m5229, 0x09, 0xef); pci_write_config_byte(&dev_m5229, 0x09, 0xef);
/* Set Primary Channel Command Block Timing */ /* Set Primary Channel Command Block Timing */
pci_write_config_byte(&dev_m5229, 0x59, 0x31); pci_write_config_byte(&dev_m5229, 0x59, 0x31);
/* /*
* Enable primary channel 40-pin cable * Enable primary channel 40-pin cable
* M5229 register 0x4a (bit 0) * M5229 register 0x4a (bit 0)
*/ */
......
...@@ -253,7 +253,7 @@ static inline void dec_kn03_be_init(void) ...@@ -253,7 +253,7 @@ static inline void dec_kn03_be_init(void)
kn0x_erraddr = (void *)(KN03_SLOT_BASE + IOASIC_ERRADDR); kn0x_erraddr = (void *)(KN03_SLOT_BASE + IOASIC_ERRADDR);
kn0x_chksyn = (void *)(KN03_SLOT_BASE + IOASIC_CHKSYN); kn0x_chksyn = (void *)(KN03_SLOT_BASE + IOASIC_CHKSYN);
/* /*
* Set normal ECC detection and generation, enable ECC correction. * Set normal ECC detection and generation, enable ECC correction.
* For KN05 we also need to make sure EE (?) is enabled in the MB. * For KN05 we also need to make sure EE (?) is enabled in the MB.
......
...@@ -129,7 +129,7 @@ static void __init it8172_setup(void) ...@@ -129,7 +129,7 @@ static void __init it8172_setup(void)
/* /*
* IO/MEM resources. * IO/MEM resources.
* *
* revisit this area. * revisit this area.
*/ */
set_io_port_base(KSEG1); set_io_port_base(KSEG1);
......
...@@ -72,7 +72,7 @@ static inline int rtc_dm_binary(void) { return saved_control & RTC_DM_BINARY; } ...@@ -72,7 +72,7 @@ static inline int rtc_dm_binary(void) { return saved_control & RTC_DM_BINARY; }
static inline unsigned char static inline unsigned char
bin_to_hw(unsigned char c) bin_to_hw(unsigned char c)
{ {
if (rtc_dm_binary()) if (rtc_dm_binary())
return c; return c;
else else
return ((c/10) << 4) + (c%10); return ((c/10) << 4) + (c%10);
...@@ -91,9 +91,9 @@ hw_to_bin(unsigned char c) ...@@ -91,9 +91,9 @@ hw_to_bin(unsigned char c)
static inline unsigned char static inline unsigned char
hour_bin_to_hw(unsigned char c) hour_bin_to_hw(unsigned char c)
{ {
if (rtc_24h()) if (rtc_24h())
return bin_to_hw(c); return bin_to_hw(c);
if (c >= 12) if (c >= 12)
return 0x80 | bin_to_hw((c==12)?12:c-12); /* 12 is 12pm */ return 0x80 | bin_to_hw((c==12)?12:c-12); /* 12 is 12pm */
else else
return bin_to_hw((c==0)?12:c); /* 0 is 12 AM, not 0 am */ return bin_to_hw((c==0)?12:c); /* 0 is 12 AM, not 0 am */
...@@ -105,9 +105,9 @@ hour_hw_to_bin(unsigned char c) ...@@ -105,9 +105,9 @@ hour_hw_to_bin(unsigned char c)
unsigned char tmp = hw_to_bin(c&0x3f); unsigned char tmp = hw_to_bin(c&0x3f);
if (rtc_24h()) if (rtc_24h())
return tmp; return tmp;
if (c & 0x80) if (c & 0x80)
return (tmp==12)?12:tmp+12; /* 12pm is 12, not 24 */ return (tmp==12)?12:tmp+12; /* 12pm is 12, not 24 */
else else
return (tmp==12)?0:tmp; /* 12am is 0 */ return (tmp==12)?0:tmp; /* 12am is 0 */
} }
...@@ -145,7 +145,7 @@ static unsigned long __init cal_r4koff(void) ...@@ -145,7 +145,7 @@ static unsigned long __init cal_r4koff(void)
return (mips_hpt_frequency / HZ); return (mips_hpt_frequency / HZ);
} }
static unsigned long static unsigned long
it8172_rtc_get_time(void) it8172_rtc_get_time(void)
{ {
unsigned int year, mon, day, hour, min, sec; unsigned int year, mon, day, hour, min, sec;
...@@ -166,12 +166,12 @@ it8172_rtc_get_time(void) ...@@ -166,12 +166,12 @@ it8172_rtc_get_time(void)
hour = hour_hw_to_bin(CMOS_READ(RTC_HOURS)); hour = hour_hw_to_bin(CMOS_READ(RTC_HOURS));
day = hw_to_bin(CMOS_READ(RTC_DAY_OF_MONTH)); day = hw_to_bin(CMOS_READ(RTC_DAY_OF_MONTH));
mon = hw_to_bin(CMOS_READ(RTC_MONTH)); mon = hw_to_bin(CMOS_READ(RTC_MONTH));
year = hw_to_bin(CMOS_READ(RTC_YEAR)) + year = hw_to_bin(CMOS_READ(RTC_YEAR)) +
hw_to_bin(*rtc_century_reg) * 100; hw_to_bin(*rtc_century_reg) * 100;
/* restore interrupts */ /* restore interrupts */
local_irq_restore(flags); local_irq_restore(flags);
return mktime(year, mon, day, hour, min, sec); return mktime(year, mon, day, hour, min, sec);
} }
......
...@@ -103,7 +103,7 @@ jiffies_to_compat_timeval(unsigned long jiffies, struct compat_timeval *value) ...@@ -103,7 +103,7 @@ jiffies_to_compat_timeval(unsigned long jiffies, struct compat_timeval *value)
* Convert jiffies to nanoseconds and seperate with * Convert jiffies to nanoseconds and seperate with
* one divide. * one divide.
*/ */
u64 nsec = (u64)jiffies * TICK_NSEC; u64 nsec = (u64)jiffies * TICK_NSEC;
value->tv_sec = div_long_long_rem(nsec, NSEC_PER_SEC, &value->tv_usec); value->tv_sec = div_long_long_rem(nsec, NSEC_PER_SEC, &value->tv_usec);
value->tv_usec /= NSEC_PER_USEC; value->tv_usec /= NSEC_PER_USEC;
} }
......