Commit 4029632c authored by Linus Torvalds's avatar Linus Torvalds

Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus

Pull more MIPS updates from Ralf Baechle:
 "This is the secondnd batch of MIPS patches for 4.7. Summary:

  CPS:
   - Copy EVA configuration when starting secondary VPs.

  EIC:
   - Clear Status IPL.

  Lasat:
   - Fix a few off by one bugs.

  lib:
   - Mark intrinsics notrace.  Not only are the intrinsics
     uninteresting, it would cause infinite recursion.

  MAINTAINERS:
   - Add file patterns for MIPS BRCM device tree bindings.
   - Add file patterns for mips device tree bindings.

  MT7628:
   - Fix MT7628 pinmux typos.
   - wled_an pinmux gpio.
   - EPHY LEDs pinmux support.

  Pistachio:
   - Enable KASLR

  VDSO:
   - Build microMIPS VDSO for microMIPS kernels.
   - Fix aliasing warning by building with `-fno-strict-aliasing' for
     debugging but also tracing them might result in recursion.

  Misc:
   - Add missing FROZEN hotplug notifier transitions.
   - Fix clk binding example for varioius PIC32 devices.
   - Fix cpu interrupt controller node-names in the DT files.
   - Fix XPA CPU feature separation.
   - Fix write_gc0_* macros when writing zero.
   - Add inline asm encoding helpers.
   - Add missing VZ accessor microMIPS encodings.
   - Fix little endian microMIPS MSA encodings.
   - Add 64-bit HTW fields and fix its configuration.
   - Fix sigreturn via VDSO on microMIPS kernel.
   - Lots of typo fixes.
   - Add definitions of SegCtl registers and use them"

* 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (49 commits)
  MIPS: Add missing FROZEN hotplug notifier transitions
  MIPS: Build microMIPS VDSO for microMIPS kernels
  MIPS: Fix sigreturn via VDSO on microMIPS kernel
  MIPS: devicetree: fix cpu interrupt controller node-names
  MIPS: VDSO: Build with `-fno-strict-aliasing'
  MIPS: Pistachio: Enable KASLR
  MIPS: lib: Mark intrinsics notrace
  MIPS: Fix 64-bit HTW configuration
  MIPS: Add 64-bit HTW fields
  MAINTAINERS: Add file patterns for mips device tree bindings
  MAINTAINERS: Add file patterns for mips brcm device tree bindings
  MIPS: Simplify DSP instruction encoding macros
  MIPS: Add missing tlbinvf/XPA microMIPS encodings
  MIPS: Fix little endian microMIPS MSA encodings
  MIPS: Add missing VZ accessor microMIPS encodings
  MIPS: Add inline asm encoding helpers
  MIPS: Spelling fix lets -> let's
  MIPS: VR41xx: Fix typo
  MIPS: oprofile: Fix typo
  MIPS: math-emu: Fix typo
  ...
parents d66492bc a8c5ddf0
......@@ -33,7 +33,7 @@ gpio0: gpio0@1f860000 {
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&PBCLK4>;
clocks = <&rootclk PB4CLK>;
microchip,gpio-bank = <0>;
gpio-ranges = <&pic32_pinctrl 0 0 16>;
};
......
......@@ -13,7 +13,7 @@ Required properties:
- compatible : Should be "mti,cpu-interrupt-controller"
Example devicetree:
cpu-irq: cpu-irq@0 {
cpu-irq: cpu-irq {
#address-cells = <0>;
interrupt-controller;
......
......@@ -20,7 +20,7 @@ Example:
compatible = "microchip,pic32mzda-sdhci";
reg = <0x1f8ec000 0x100>;
interrupts = <191 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&REFCLKO4>, <&PBCLK5>;
clocks = <&rootclk REF4CLK>, <&rootclk PB5CLK>;
clock-names = "base_clk", "sys_clk";
bus-width = <4>;
cap-sd-highspeed;
......
......@@ -34,7 +34,7 @@ pic32_pinctrl: pinctrl@1f801400{
#size-cells = <1>;
compatible = "microchip,pic32mzda-pinctrl";
reg = <0x1f801400 0x400>;
clocks = <&PBCLK1>;
clocks = <&rootclk PB1CLK>;
pinctrl_uart2: pinctrl_uart2 {
uart2-tx {
......
......@@ -20,7 +20,7 @@ Example:
interrupts = <112 IRQ_TYPE_LEVEL_HIGH>,
<113 IRQ_TYPE_LEVEL_HIGH>,
<114 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&PBCLK2>;
clocks = <&rootclk PB2CLK>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1
&pinctrl_uart1_cts
......
......@@ -8,12 +8,12 @@ Required properties:
- compatible: must be "microchip,pic32mzda-dmt".
- reg: physical base address of the controller and length of memory mapped
region.
- clocks: phandle of parent clock (should be &PBCLK7).
- clocks: phandle of source clk. Should be <&rootclk PB7CLK>.
Example:
watchdog@1f800a00 {
compatible = "microchip,pic32mzda-dmt";
reg = <0x1f800a00 0x80>;
clocks = <&PBCLK7>;
clocks = <&rootclk PB7CLK>;
};
......@@ -7,12 +7,12 @@ Required properties:
- compatible: must be "microchip,pic32mzda-wdt".
- reg: physical base address of the controller and length of memory mapped
region.
- clocks: phandle of source clk. should be <&LPRC> clk.
- clocks: phandle of source clk. Should be <&rootclk LPRCCLK>.
Example:
watchdog@1f800800 {
compatible = "microchip,pic32mzda-wdt";
reg = <0x1f800800 0x200>;
clocks = <&LPRC>;
clocks = <&rootclk LPRCCLK>;
};
......@@ -2505,6 +2505,7 @@ M: Hauke Mehrtens <hauke@hauke-m.de>
M: Rafał Miłecki <zajec5@gmail.com>
L: linux-mips@linux-mips.org
S: Maintained
F: Documentation/devicetree/bindings/mips/brcm/
F: arch/mips/bcm47xx/*
F: arch/mips/include/asm/mach-bcm47xx/*
......@@ -7521,6 +7522,7 @@ W: http://www.linux-mips.org/
T: git git://git.linux-mips.org/pub/scm/ralf/linux.git
Q: http://patchwork.linux-mips.org/project/linux-mips/list/
S: Supported
F: Documentation/devicetree/bindings/mips/
F: Documentation/mips/
F: arch/mips/
......
......@@ -398,6 +398,7 @@ config MACH_PISTACHIO
select SYS_SUPPORTS_LITTLE_ENDIAN
select SYS_SUPPORTS_MIPS_CPS
select SYS_SUPPORTS_MULTITHREADING
select SYS_SUPPORTS_RELOCATABLE
select SYS_SUPPORTS_ZBOOT
select SYS_HAS_EARLY_PRINTK
select USE_GENERIC_EARLY_PRINTK_8250
......
......@@ -5,7 +5,7 @@
#size-cells = <1>;
compatible = "ingenic,jz4740";
cpuintc: interrupt-controller@0 {
cpuintc: interrupt-controller {
#address-cells = <0>;
#interrupt-cells = <1>;
interrupt-controller;
......
......@@ -9,7 +9,7 @@
};
};
cpuintc: cpuintc@0 {
cpuintc: cpuintc {
#address-cells = <0>;
#interrupt-cells = <1>;
interrupt-controller;
......
......@@ -9,7 +9,7 @@
};
};
cpuintc: cpuintc@0 {
cpuintc: cpuintc {
#address-cells = <0>;
#interrupt-cells = <1>;
interrupt-controller;
......
......@@ -9,7 +9,7 @@
};
};
cpuintc: cpuintc@0 {
cpuintc: cpuintc {
#address-cells = <0>;
#interrupt-cells = <1>;
interrupt-controller;
......
......@@ -9,7 +9,7 @@
};
};
cpuintc: cpuintc@0 {
cpuintc: cpuintc {
#address-cells = <0>;
#interrupt-cells = <1>;
interrupt-controller;
......
......@@ -10,7 +10,7 @@
reg = <0x0 0x08000000>;
};
cpuintc: interrupt-controller@0 {
cpuintc: interrupt-controller {
#address-cells = <0>;
#interrupt-cells = <1>;
interrupt-controller;
......
......@@ -384,7 +384,7 @@ static int octeon_cpu_callback(struct notifier_block *nfb,
{
unsigned int cpu = (unsigned long)hcpu;
switch (action) {
switch (action & ~CPU_TASKS_FROZEN) {
case CPU_UP_PREPARE:
octeon_update_boot_vector(cpu);
break;
......
......@@ -19,6 +19,28 @@
#include <asm/asmmacro-64.h>
#endif
/*
* Helper macros for generating raw instruction encodings.
*/
#ifdef CONFIG_CPU_MICROMIPS
.macro insn32_if_mm enc
.insn
.hword ((\enc) >> 16)
.hword ((\enc) & 0xffff)
.endm
.macro insn_if_mips enc
.endm
#else
.macro insn32_if_mm enc
.endm
.macro insn_if_mips enc
.insn
.word (\enc)
.endm
#endif
#if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6)
.macro local_irq_enable reg=t0
ei
......@@ -341,38 +363,6 @@
.endm
#else
#ifdef CONFIG_CPU_MICROMIPS
#define CFC_MSA_INSN 0x587e0056
#define CTC_MSA_INSN 0x583e0816
#define LDB_MSA_INSN 0x58000807
#define LDH_MSA_INSN 0x58000817
#define LDW_MSA_INSN 0x58000827
#define LDD_MSA_INSN 0x58000837
#define STB_MSA_INSN 0x5800080f
#define STH_MSA_INSN 0x5800081f
#define STW_MSA_INSN 0x5800082f
#define STD_MSA_INSN 0x5800083f
#define COPY_SW_MSA_INSN 0x58b00056
#define COPY_SD_MSA_INSN 0x58b80056
#define INSERT_W_MSA_INSN 0x59300816
#define INSERT_D_MSA_INSN 0x59380816
#else
#define CFC_MSA_INSN 0x787e0059
#define CTC_MSA_INSN 0x783e0819
#define LDB_MSA_INSN 0x78000820
#define LDH_MSA_INSN 0x78000821
#define LDW_MSA_INSN 0x78000822
#define LDD_MSA_INSN 0x78000823
#define STB_MSA_INSN 0x78000824
#define STH_MSA_INSN 0x78000825
#define STW_MSA_INSN 0x78000826
#define STD_MSA_INSN 0x78000827
#define COPY_SW_MSA_INSN 0x78b00059
#define COPY_SD_MSA_INSN 0x78b80059
#define INSERT_W_MSA_INSN 0x79300819
#define INSERT_D_MSA_INSN 0x79380819
#endif
/*
* Temporary until all toolchains in use include MSA support.
*/
......@@ -380,8 +370,8 @@
.set push
.set noat
SET_HARDFLOAT
.insn
.word CFC_MSA_INSN | (\cs << 11)
insn_if_mips 0x787e0059 | (\cs << 11)
insn32_if_mm 0x587e0056 | (\cs << 11)
move \rd, $1
.set pop
.endm
......@@ -391,7 +381,8 @@
.set noat
SET_HARDFLOAT
move $1, \rs
.word CTC_MSA_INSN | (\cd << 6)
insn_if_mips 0x783e0819 | (\cd << 6)
insn32_if_mm 0x583e0816 | (\cd << 6)
.set pop
.endm
......@@ -400,7 +391,8 @@
.set noat
SET_HARDFLOAT
PTR_ADDU $1, \base, \off
.word LDB_MSA_INSN | (\wd << 6)
insn_if_mips 0x78000820 | (\wd << 6)
insn32_if_mm 0x58000807 | (\wd << 6)
.set pop
.endm
......@@ -409,7 +401,8 @@
.set noat
SET_HARDFLOAT
PTR_ADDU $1, \base, \off
.word LDH_MSA_INSN | (\wd << 6)
insn_if_mips 0x78000821 | (\wd << 6)
insn32_if_mm 0x58000817 | (\wd << 6)
.set pop
.endm
......@@ -418,7 +411,8 @@
.set noat
SET_HARDFLOAT
PTR_ADDU $1, \base, \off
.word LDW_MSA_INSN | (\wd << 6)
insn_if_mips 0x78000822 | (\wd << 6)
insn32_if_mm 0x58000827 | (\wd << 6)
.set pop
.endm
......@@ -427,7 +421,8 @@
.set noat
SET_HARDFLOAT
PTR_ADDU $1, \base, \off
.word LDD_MSA_INSN | (\wd << 6)
insn_if_mips 0x78000823 | (\wd << 6)
insn32_if_mm 0x58000837 | (\wd << 6)
.set pop
.endm
......@@ -436,7 +431,8 @@
.set noat
SET_HARDFLOAT
PTR_ADDU $1, \base, \off
.word STB_MSA_INSN | (\wd << 6)
insn_if_mips 0x78000824 | (\wd << 6)
insn32_if_mm 0x5800080f | (\wd << 6)
.set pop
.endm
......@@ -445,7 +441,8 @@
.set noat
SET_HARDFLOAT
PTR_ADDU $1, \base, \off
.word STH_MSA_INSN | (\wd << 6)
insn_if_mips 0x78000825 | (\wd << 6)
insn32_if_mm 0x5800081f | (\wd << 6)
.set pop
.endm
......@@ -454,7 +451,8 @@
.set noat
SET_HARDFLOAT
PTR_ADDU $1, \base, \off
.word STW_MSA_INSN | (\wd << 6)
insn_if_mips 0x78000826 | (\wd << 6)
insn32_if_mm 0x5800082f | (\wd << 6)
.set pop
.endm
......@@ -463,7 +461,8 @@
.set noat
SET_HARDFLOAT
PTR_ADDU $1, \base, \off
.word STD_MSA_INSN | (\wd << 6)
insn_if_mips 0x78000827 | (\wd << 6)
insn32_if_mm 0x5800083f | (\wd << 6)
.set pop
.endm
......@@ -471,8 +470,8 @@
.set push
.set noat
SET_HARDFLOAT
.insn
.word COPY_SW_MSA_INSN | (\n << 16) | (\ws << 11)
insn_if_mips 0x78b00059 | (\n << 16) | (\ws << 11)
insn32_if_mm 0x58b00056 | (\n << 16) | (\ws << 11)
.set pop
.endm
......@@ -480,8 +479,8 @@
.set push
.set noat
SET_HARDFLOAT
.insn
.word COPY_SD_MSA_INSN | (\n << 16) | (\ws << 11)
insn_if_mips 0x78b80059 | (\n << 16) | (\ws << 11)
insn32_if_mm 0x58b80056 | (\n << 16) | (\ws << 11)
.set pop
.endm
......@@ -489,7 +488,8 @@
.set push
.set noat
SET_HARDFLOAT
.word INSERT_W_MSA_INSN | (\n << 16) | (\wd << 6)
insn_if_mips 0x79300819 | (\n << 16) | (\wd << 6)
insn32_if_mm 0x59300816 | (\n << 16) | (\wd << 6)
.set pop
.endm
......@@ -497,7 +497,8 @@
.set push
.set noat
SET_HARDFLOAT
.word INSERT_D_MSA_INSN | (\n << 16) | (\wd << 6)
insn_if_mips 0x79380819 | (\n << 16) | (\wd << 6)
insn32_if_mm 0x59380816 | (\n << 16) | (\wd << 6)
.set pop
.endm
#endif
......
......@@ -58,8 +58,8 @@
* address of a label as argument to inline assembler. Gas otoh has the
* annoying difference between la and dla which are only usable for 32-bit
* rsp. 64-bit code, so can't be used without conditional compilation.
* The alterantive is switching the assembler to 64-bit code which happens
* to work right even for 32-bit code ...
* The alternative is switching the assembler to 64-bit code which happens
* to work right even for 32-bit code...
*/
#define instruction_hazard() \
do { \
......@@ -133,8 +133,8 @@ do { \
* address of a label as argument to inline assembler. Gas otoh has the
* annoying difference between la and dla which are only usable for 32-bit
* rsp. 64-bit code, so can't be used without conditional compilation.
* The alterantive is switching the assembler to 64-bit code which happens
* to work right even for 32-bit code ...
* The alternative is switching the assembler to 64-bit code which happens
* to work right even for 32-bit code...
*/
#define __instruction_hazard() \
do { \
......
......@@ -100,7 +100,7 @@ typedef volatile struct au1xxx_ddma_desc {
u32 dscr_nxtptr; /* Next descriptor pointer (mostly) */
/*
* First 32 bytes are HW specific!!!
* Lets have some SW data following -- make sure it's 32 bytes.
* Let's have some SW data following -- make sure it's 32 bytes.
*/
u32 sw_status;
u32 sw_context;
......
......@@ -140,7 +140,7 @@ static inline int au1300_gpio_getinitlvl(unsigned int gpio)
* Cases 1 and 3 are intended for boards which want to provide their own
* GPIO namespace and -operations (i.e. for example you have 8 GPIOs
* which are in part provided by spare Au1300 GPIO pins and in part by
* an external FPGA but you still want them to be accssible in linux
* an external FPGA but you still want them to be accessible in linux
* as gpio0-7. The board can of course use the alchemy_gpioX_* functions
* as required).
*/
......
......@@ -22,7 +22,7 @@ struct bcm63xx_enet_platform_data {
int has_phy_interrupt;
int phy_interrupt;
/* if has_phy, use autonegociated pause parameters or force
/* if has_phy, use autonegotiated pause parameters or force
* them */
int pause_auto;
int pause_rx;
......
......@@ -64,7 +64,7 @@ static inline void plat_post_dma_flush(struct device *dev)
static inline int plat_device_is_coherent(struct device *dev)
{
return 1; /* IP27 non-cohernet mode is unsupported */
return 1; /* IP27 non-coherent mode is unsupported */
}
#endif /* __ASM_MACH_IP27_DMA_COHERENCE_H */
......@@ -86,7 +86,7 @@ static inline void plat_post_dma_flush(struct device *dev)
static inline int plat_device_is_coherent(struct device *dev)
{
return 0; /* IP32 is non-cohernet */
return 0; /* IP32 is non-coherent */
}
#endif /* __ASM_MACH_IP32_DMA_COHERENCE_H */
......@@ -22,7 +22,7 @@
/*
* during early_printk no ioremap possible at this early stage
* lets use KSEG1 instead
* let's use KSEG1 instead
*/
#define LTQ_ASC0_BASE_ADDR 0x1E100C00
#define LTQ_EARLY_ASC KSEG1ADDR(LTQ_ASC0_BASE_ADDR)
......
......@@ -75,7 +75,7 @@ extern __iomem void *ltq_cgu_membase;
/*
* during early_printk no ioremap is possible
* lets use KSEG1 instead
* let's use KSEG1 instead
*/
#define LTQ_ASC1_BASE_ADDR 0x1E100C00
#define LTQ_EARLY_ASC KSEG1ADDR(LTQ_ASC1_BASE_ADDR)
......
......@@ -24,7 +24,7 @@ struct temp_range {
u8 level;
};
#define CONSTANT_SPEED_POLICY 0 /* at constent speed */
#define CONSTANT_SPEED_POLICY 0 /* at constant speed */
#define STEP_SPEED_POLICY 1 /* use up/down arrays to describe policy */
#define KERNEL_HELPER_POLICY 2 /* kernel as a helper to fan control */
......
......@@ -56,7 +56,7 @@
(0 << MIPS_SEGCFG_PA_SHIFT) | \
(1 << MIPS_SEGCFG_EU_SHIFT)) << 16)
or t0, t2
mtc0 t0, $5, 2
mtc0 t0, CP0_SEGCTL0
/* SegCtl1 */
li t0, ((MIPS_SEGCFG_MUSUK << MIPS_SEGCFG_AM_SHIFT) | \
......@@ -67,7 +67,7 @@
(0 << MIPS_SEGCFG_PA_SHIFT) | \
(1 << MIPS_SEGCFG_EU_SHIFT)) << 16)
ins t0, t1, 16, 3
mtc0 t0, $5, 3
mtc0 t0, CP0_SEGCTL1
/* SegCtl2 */
li t0, ((MIPS_SEGCFG_MUSUK << MIPS_SEGCFG_AM_SHIFT) | \
......@@ -77,7 +77,7 @@
(4 << MIPS_SEGCFG_PA_SHIFT) | \
(1 << MIPS_SEGCFG_EU_SHIFT)) << 16)
or t0, t2
mtc0 t0, $5, 4
mtc0 t0, CP0_SEGCTL2
jal mips_ihb
mfc0 t0, $16, 5
......
/*
* Definitions and decalrations for MIPS MT support that are common between
* Definitions and declarations for MIPS MT support that are common between
* the VSMP, and AP/SP kernel models.
*/
#ifndef __ASM_MIPS_MT_H
......
......@@ -48,6 +48,9 @@
#define CP0_CONF $3
#define CP0_CONTEXT $4
#define CP0_PAGEMASK $5
#define CP0_SEGCTL0 $5, 2
#define CP0_SEGCTL1 $5, 3
#define CP0_SEGCTL2 $5, 4
#define CP0_WIRED $6
#define CP0_INFO $7
#define CP0_HWRENA $7, 0
......@@ -726,6 +729,8 @@
#define MIPS_PWFIELD_PTEI_SHIFT 0
#define MIPS_PWFIELD_PTEI_MASK 0x0000003f
#define MIPS_PWSIZE_PS_SHIFT 30
#define MIPS_PWSIZE_PS_MASK 0x40000000
#define MIPS_PWSIZE_GDW_SHIFT 24
#define MIPS_PWSIZE_GDW_MASK 0x3f000000
#define MIPS_PWSIZE_UDW_SHIFT 18
......@@ -739,6 +744,12 @@
#define MIPS_PWCTL_PWEN_SHIFT 31
#define MIPS_PWCTL_PWEN_MASK 0x80000000
#define MIPS_PWCTL_XK_SHIFT 28
#define MIPS_PWCTL_XK_MASK 0x10000000
#define MIPS_PWCTL_XS_SHIFT 27
#define MIPS_PWCTL_XS_MASK 0x08000000
#define MIPS_PWCTL_XU_SHIFT 26
#define MIPS_PWCTL_XU_MASK 0x04000000
#define MIPS_PWCTL_DPH_SHIFT 7
#define MIPS_PWCTL_DPH_MASK 0x00000080
#define MIPS_PWCTL_HUGEPG_SHIFT 6
......@@ -1045,6 +1056,33 @@ static inline int mm_insn_16bit(u16 insn)
return (opcode >= 1 && opcode <= 3) ? 1 : 0;
}
/*
* Helper macros for generating raw instruction encodings in inline asm.
*/
#ifdef CONFIG_CPU_MICROMIPS
#define _ASM_INSN16_IF_MM(_enc) \
".insn\n\t" \
".hword (" #_enc ")\n\t"
#define _ASM_INSN32_IF_MM(_enc) \
".insn\n\t" \
".hword ((" #_enc ") >> 16)\n\t" \
".hword ((" #_enc ") & 0xffff)\n\t"
#else
#define _ASM_INSN_IF_MIPS(_enc) \
".insn\n\t" \
".word (" #_enc ")\n\t"
#endif
#ifndef _ASM_INSN16_IF_MM
#define _ASM_INSN16_IF_MM(_enc)
#endif
#ifndef _ASM_INSN32_IF_MM
#define _ASM_INSN32_IF_MM(_enc)
#endif
#ifndef _ASM_INSN_IF_MIPS
#define _ASM_INSN_IF_MIPS(_enc)
#endif
/*
* TLB Invalidate Flush
*/
......@@ -1053,7 +1091,9 @@ static inline void tlbinvf(void)
__asm__ __volatile__(
".set push\n\t"
".set noreorder\n\t"
".word 0x42000004\n\t" /* tlbinvf */
"# tlbinvf\n\t"
_ASM_INSN_IF_MIPS(0x42000004)
_ASM_INSN32_IF_MM(0x0000537c)
".set pop");
}
......@@ -1274,9 +1314,9 @@ do { \
" .set push \n" \
" .set noat \n" \
" .set mips32r2 \n" \
" .insn \n" \
" # mfhc0 $1, %1 \n" \
" .word (0x40410000 | ((%1 & 0x1f) << 11)) \n" \
_ASM_INSN_IF_MIPS(0x40410000 | ((%1 & 0x1f) << 11)) \
_ASM_INSN32_IF_MM(0x002000f4 | ((%1 & 0x1f) << 16)) \
" move %0, $1 \n" \
" .set pop \n" \
: "=r" (__res) \
......@@ -1292,8 +1332,8 @@ do { \
" .set mips32r2 \n" \