Commit 0c23664e authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge master.kernel.org:/pub/scm/linux/kernel/git/davem/sparc-2.6

* master.kernel.org:/pub/scm/linux/kernel/git/davem/sparc-2.6:
  [SPARC64]: Optimize fault kprobe handling just like powerpc.
  [SPARC]: Wire up utimensat syscall.
  [SPARC64]: Fix request_irq() ignored result warnings in PCI controller code.
  [SPARC64]: Kill asm-sparc64/pbm.h
  [ATYFB]: Fix sparc includes.
  [QLA2XXX]: Fix build on sparc.
  [SPARC64]: Removal of trivial pci_controller_info uses.
  [SPARC64]: Move index info pci_pbm_info.
  [SPARC64]: Move {setup,teardown}_msi_irq into pci_pbm_info.
  [SPARC64]: Move pci_ops into pci_pbm_info.
  [SPARC64] SBUS: Error interrupt registry cleanups.
  [SPARC64] PCI: Use root list of pbm's instead of pci_controller_info's
  [SPARC64] PCI: Kill PROM_PCIRNG_MAX and PROM_PCIIMAP_MAX.
  [SPARC64] PCI: Use common routine to fetch PBM properties.
parents 6ec129c3 127cda1e
......@@ -80,6 +80,7 @@ sys_call_table:
/*295*/ .long sys_fchmodat, sys_faccessat, sys_pselect6, sys_ppoll, sys_unshare
/*300*/ .long sys_set_robust_list, sys_get_robust_list, sys_migrate_pages, sys_mbind, sys_get_mempolicy
/*305*/ .long sys_set_mempolicy, sys_kexec_load, sys_move_pages, sys_getcpu, sys_epoll_pwait
/*310*/ .long sys_utimensat
#ifdef CONFIG_SUNOS_EMUL
/* Now the SunOS syscall table. */
......@@ -196,5 +197,6 @@ sunos_sys_table:
.long sunos_nosys, sunos_nosys, sunos_nosys
.long sunos_nosys, sunos_nosys, sunos_nosys
.long sunos_nosys
/*310*/ .long sunos_nosys
#endif
......@@ -13,16 +13,17 @@
#include <linux/string.h>
#include <linux/interrupt.h>
#include <linux/delay.h>
#include <linux/pci.h>
#include <asm/system.h>
#include <asm/page.h>
#include <asm/pbm.h>
#include <asm/ebus.h>
#include <asm/oplib.h>
#include <asm/prom.h>
#include <asm/of_device.h>
#include <asm/bpp.h>
#include <asm/irq.h>
#include <asm/io.h>
/* EBUS dma library. */
......
......@@ -313,7 +313,7 @@ out:
return 1;
}
static int __kprobes kprobe_fault_handler(struct pt_regs *regs, int trapnr)
int __kprobes kprobe_fault_handler(struct pt_regs *regs, int trapnr)
{
struct kprobe *cur = kprobe_running();
struct kprobe_ctlblk *kcb = get_kprobe_ctlblk();
......@@ -403,15 +403,6 @@ int __kprobes kprobe_exceptions_notify(struct notifier_block *self,
if (post_kprobe_handler(args->regs))
ret = NOTIFY_STOP;
break;
case DIE_GPF:
case DIE_PAGE_FAULT:
/* kprobe_running() needs smp_processor_id() */
preempt_disable();
if (kprobe_running() &&
kprobe_fault_handler(args->regs, args->trapnr))
ret = NOTIFY_STOP;
preempt_enable();
break;
default:
break;
}
......
......@@ -14,12 +14,12 @@
#include <linux/sched.h>
#include <linux/capability.h>
#include <linux/errno.h>
#include <linux/pci.h>
#include <linux/msi.h>
#include <linux/irq.h>
#include <linux/init.h>
#include <asm/uaccess.h>
#include <asm/pbm.h>
#include <asm/pgtable.h>
#include <asm/irq.h>
#include <asm/ebus.h>
......@@ -48,10 +48,10 @@ asmlinkage int sys_pciconfig_write(unsigned long bus, unsigned long dfn,
#else
/* List of all PCI controllers found in the system. */
struct pci_controller_info *pci_controller_root = NULL;
struct pci_pbm_info *pci_pbm_root = NULL;
/* Each PCI controller found gets a unique index. */
int pci_num_controllers = 0;
/* Each PBM found gets a unique index. */
int pci_num_pbms = 0;
volatile int pci_poke_in_progress;
volatile int pci_poke_cpu = -1;
......@@ -291,7 +291,7 @@ extern const struct pci_iommu_ops pci_sun4u_iommu_ops,
/* Find each controller in the system, attach and initialize
* software state structure for each and link into the
* pci_controller_root. Setup the controller enough such
* pci_pbm_root. Setup the controller enough such
* that bus scanning can be done.
*/
static void __init pci_controller_probe(void)
......@@ -743,7 +743,6 @@ int pci_host_bridge_write_pci_cfg(struct pci_bus *bus_dev,
struct pci_bus * __devinit pci_scan_one_pbm(struct pci_pbm_info *pbm)
{
struct pci_controller_info *p = pbm->parent;
struct device_node *node = pbm->prom_node;
struct pci_dev *host_pdev;
struct pci_bus *bus;
......@@ -751,7 +750,7 @@ struct pci_bus * __devinit pci_scan_one_pbm(struct pci_pbm_info *pbm)
printk("PCI: Scanning PBM %s\n", node->full_name);
/* XXX parent device? XXX */
bus = pci_create_bus(NULL, pbm->pci_first_busno, p->pci_ops, pbm);
bus = pci_create_bus(NULL, pbm->pci_first_busno, pbm->pci_ops, pbm);
if (!bus) {
printk(KERN_ERR "Failed to create bus for %s\n",
node->full_name);
......@@ -776,10 +775,10 @@ struct pci_bus * __devinit pci_scan_one_pbm(struct pci_pbm_info *pbm)
static void __init pci_scan_each_controller_bus(void)
{
struct pci_controller_info *p;
struct pci_pbm_info *pbm;
for (p = pci_controller_root; p; p = p->next)
p->scan_bus(p);
for (pbm = pci_pbm_root; pbm; pbm = pbm->next)
pbm->scan_bus(pbm);
}
extern void power_init(void);
......@@ -787,7 +786,7 @@ extern void power_init(void);
static int __init pcibios_init(void)
{
pci_controller_probe();
if (pci_controller_root == NULL)
if (pci_pbm_root == NULL)
return 0;
pci_scan_each_controller_bus();
......@@ -922,10 +921,8 @@ static int __pci_mmap_make_offset_bus(struct pci_dev *pdev, struct vm_area_struc
enum pci_mmap_state mmap_state)
{
struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller;
struct pci_controller_info *p;
unsigned long space_size, user_offset, user_size;
p = pbm->parent;
if (mmap_state == pci_mmap_io) {
space_size = (pbm->io_space.end -
pbm->io_space.start) + 1;
......@@ -1078,11 +1075,7 @@ int pci_domain_nr(struct pci_bus *pbus)
if (pbm == NULL || pbm->parent == NULL) {
ret = -ENXIO;
} else {
struct pci_controller_info *p = pbm->parent;
ret = p->index;
ret = ((ret << 1) +
((pbm == &pbm->parent->pbm_B) ? 1 : 0));
ret = pbm->index;
}
return ret;
......@@ -1093,17 +1086,12 @@ EXPORT_SYMBOL(pci_domain_nr);
int arch_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc)
{
struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller;
struct pci_controller_info *p = pbm->parent;
int virt_irq, err;
int virt_irq;
if (!pbm->msi_num || !p->setup_msi_irq)
if (!pbm->setup_msi_irq)
return -EINVAL;
err = p->setup_msi_irq(&virt_irq, pdev, desc);
if (err)
return err;
return 0;
return pbm->setup_msi_irq(&virt_irq, pdev, desc);
}
void arch_teardown_msi_irq(unsigned int virt_irq)
......@@ -1111,12 +1099,11 @@ void arch_teardown_msi_irq(unsigned int virt_irq)
struct msi_desc *entry = get_irq_msi(virt_irq);
struct pci_dev *pdev = entry->dev;
struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller;
struct pci_controller_info *p = pbm->parent;
if (!pbm->msi_num || !p->setup_msi_irq)
if (!pbm->teardown_msi_irq)
return;
return p->teardown_msi_irq(virt_irq, pdev);
return pbm->teardown_msi_irq(virt_irq, pdev);
}
#endif /* !(CONFIG_PCI_MSI) */
......
......@@ -9,12 +9,26 @@
#include <linux/pci.h>
#include <linux/device.h>
#include <asm/pbm.h>
#include <asm/prom.h>
#include <asm/of_device.h>
#include <asm/oplib.h>
#include "pci_impl.h"
void pci_get_pbm_props(struct pci_pbm_info *pbm)
{
const u32 *val = of_get_property(pbm->prom_node, "bus-range", NULL);
pbm->pci_first_busno = val[0];
pbm->pci_last_busno = val[1];
val = of_get_property(pbm->prom_node, "ino-bitmap", NULL);
if (val) {
pbm->ino_bitmap = (((u64)val[1] << 32UL) |
((u64)val[0] << 0UL));
}
}
static void pci_register_legacy_regions(struct resource *io_res,
struct resource *mem_res)
{
......@@ -149,8 +163,7 @@ void pci_determine_mem_io_space(struct pci_pbm_info *pbm)
}
/* Generic helper routines for PCI error reporting. */
void pci_scan_for_target_abort(struct pci_controller_info *p,
struct pci_pbm_info *pbm,
void pci_scan_for_target_abort(struct pci_pbm_info *pbm,
struct pci_bus *pbus)
{
struct pci_dev *pdev;
......@@ -165,18 +178,16 @@ void pci_scan_for_target_abort(struct pci_controller_info *p,
PCI_STATUS_REC_TARGET_ABORT));
if (error_bits) {
pci_write_config_word(pdev, PCI_STATUS, error_bits);
printk("PCI%d(PBM%c): Device [%s] saw Target Abort [%016x]\n",
p->index, ((pbm == &p->pbm_A) ? 'A' : 'B'),
pci_name(pdev), status);
printk("%s: Device %s saw Target Abort [%016x]\n",
pbm->name, pci_name(pdev), status);
}
}
list_for_each_entry(bus, &pbus->children, node)
pci_scan_for_target_abort(p, pbm, bus);
pci_scan_for_target_abort(pbm, bus);
}
void pci_scan_for_master_abort(struct pci_controller_info *p,
struct pci_pbm_info *pbm,
void pci_scan_for_master_abort(struct pci_pbm_info *pbm,
struct pci_bus *pbus)
{
struct pci_dev *pdev;
......@@ -190,18 +201,16 @@ void pci_scan_for_master_abort(struct pci_controller_info *p,
(status & (PCI_STATUS_REC_MASTER_ABORT));
if (error_bits) {
pci_write_config_word(pdev, PCI_STATUS, error_bits);
printk("PCI%d(PBM%c): Device [%s] received Master Abort [%016x]\n",
p->index, ((pbm == &p->pbm_A) ? 'A' : 'B'),
pci_name(pdev), status);
printk("%s: Device %s received Master Abort [%016x]\n",
pbm->name, pci_name(pdev), status);
}
}
list_for_each_entry(bus, &pbus->children, node)
pci_scan_for_master_abort(p, pbm, bus);
pci_scan_for_master_abort(pbm, bus);
}
void pci_scan_for_parity_error(struct pci_controller_info *p,
struct pci_pbm_info *pbm,
void pci_scan_for_parity_error(struct pci_pbm_info *pbm,
struct pci_bus *pbus)
{
struct pci_dev *pdev;
......@@ -216,12 +225,11 @@ void pci_scan_for_parity_error(struct pci_controller_info *p,
PCI_STATUS_DETECTED_PARITY));
if (error_bits) {
pci_write_config_word(pdev, PCI_STATUS, error_bits);
printk("PCI%d(PBM%c): Device [%s] saw Parity Error [%016x]\n",
p->index, ((pbm == &p->pbm_A) ? 'A' : 'B'),
pci_name(pdev), status);
printk("%s: Device %s saw Parity Error [%016x]\n",
pbm->name, pci_name(pdev), status);
}
}
list_for_each_entry(bus, &pbus->children, node)
pci_scan_for_parity_error(p, pbm, bus);
pci_scan_for_parity_error(pbm, bus);
}
......@@ -7,7 +7,6 @@
#include <linux/slab.h>
#include <linux/init.h>
#include <asm/pbm.h>
#include <asm/oplib.h>
#include <asm/prom.h>
......@@ -160,21 +159,9 @@ static struct pci_ops pci_fire_ops = {
.write = fire_write_pci_cfg,
};
static void pbm_scan_bus(struct pci_controller_info *p,
struct pci_pbm_info *pbm)
static void pci_fire_scan_bus(struct pci_pbm_info *pbm)
{
pbm->pci_bus = pci_scan_one_pbm(pbm);
}
static void pci_fire_scan_bus(struct pci_controller_info *p)
{
struct device_node *dp;
if ((dp = p->pbm_A.prom_node) != NULL)
pbm_scan_bus(p, &p->pbm_A);
if ((dp = p->pbm_B.prom_node) != NULL)
pbm_scan_bus(p, &p->pbm_B);
/* XXX register error interrupt handlers XXX */
}
......@@ -313,18 +300,24 @@ static void pci_fire_hw_init(struct pci_pbm_info *pbm)
}
static void pci_fire_pbm_init(struct pci_controller_info *p,
struct device_node *dp, u32 portid)
struct device_node *dp, u32 portid)
{
const struct linux_prom64_registers *regs;
struct pci_pbm_info *pbm;
const u32 *ino_bitmap;
const unsigned int *busrange;
if ((portid & 1) == 0)
pbm = &p->pbm_A;
else
pbm = &p->pbm_B;
pbm->next = pci_pbm_root;
pci_pbm_root = pbm;
pbm->scan_bus = pci_fire_scan_bus;
pbm->pci_ops = &pci_fire_ops;
pbm->index = pci_num_pbms++;
pbm->portid = portid;
pbm->parent = p;
pbm->prom_node = dp;
......@@ -338,13 +331,7 @@ static void pci_fire_pbm_init(struct pci_controller_info *p,
pci_determine_mem_io_space(pbm);
ino_bitmap = of_get_property(dp, "ino-bitmap", NULL);
pbm->ino_bitmap = (((u64)ino_bitmap[1] << 32UL) |
((u64)ino_bitmap[0] << 0UL));
busrange = of_get_property(dp, "bus-range", NULL);
pbm->pci_first_busno = busrange[0];
pbm->pci_last_busno = busrange[1];
pci_get_pbm_props(pbm);
pci_fire_hw_init(pbm);
pci_fire_pbm_iommu_init(pbm);
......@@ -362,19 +349,11 @@ void fire_pci_init(struct device_node *dp, const char *model_name)
struct pci_controller_info *p;
u32 portid = of_getintprop_default(dp, "portid", 0xff);
struct iommu *iommu;
struct pci_pbm_info *pbm;
for (p = pci_controller_root; p; p = p->next) {
struct pci_pbm_info *pbm;
if (p->pbm_A.prom_node && p->pbm_B.prom_node)
continue;
pbm = (p->pbm_A.prom_node ?
&p->pbm_A :
&p->pbm_B);
for (pbm = pci_pbm_root; pbm; pbm = pbm->next) {
if (portid_compare(pbm->portid, portid)) {
pci_fire_pbm_init(p, dp, portid);
pci_fire_pbm_init(pbm->parent, dp, portid);
return;
}
}
......@@ -395,14 +374,7 @@ void fire_pci_init(struct device_node *dp, const char *model_name)
p->pbm_B.iommu = iommu;
p->next = pci_controller_root;
pci_controller_root = p;
p->index = pci_num_controllers++;
p->scan_bus = pci_fire_scan_bus;
/* XXX MSI support XXX */
p->pci_ops = &pci_fire_ops;
/* Like PSYCHO and SCHIZO we have a 2GB aligned area
* for memory space.
......
......@@ -8,15 +8,129 @@
#include <linux/types.h>
#include <linux/spinlock.h>
#include <linux/pci.h>
#include <linux/msi.h>
#include <asm/io.h>
#include <asm/prom.h>
#include <asm/iommu.h>
extern struct pci_controller_info *pci_controller_root;
/* The abstraction used here is that there are PCI controllers,
* each with one (Sabre) or two (PSYCHO/SCHIZO) PCI bus modules
* underneath. Each PCI bus module uses an IOMMU (shared by both
* PBMs of a controller, or per-PBM), and if a streaming buffer
* is present, each PCI bus module has it's own. (ie. the IOMMU
* might be shared between PBMs, the STC is never shared)
* Furthermore, each PCI bus module controls it's own autonomous
* PCI bus.
*/
#define PCI_STC_FLUSHFLAG_INIT(STC) \
(*((STC)->strbuf_flushflag) = 0UL)
#define PCI_STC_FLUSHFLAG_SET(STC) \
(*((STC)->strbuf_flushflag) != 0UL)
struct pci_controller_info;
struct pci_pbm_info {
struct pci_pbm_info *next;
int index;
/* PCI controller we sit under. */
struct pci_controller_info *parent;
/* Physical address base of controller registers. */
unsigned long controller_regs;
/* Physical address base of PBM registers. */
unsigned long pbm_regs;
/* Physical address of DMA sync register, if any. */
unsigned long sync_reg;
/* Opaque 32-bit system bus Port ID. */
u32 portid;
/* Opaque 32-bit handle used for hypervisor calls. */
u32 devhandle;
/* Chipset version information. */
int chip_type;
#define PBM_CHIP_TYPE_SABRE 1
#define PBM_CHIP_TYPE_PSYCHO 2
#define PBM_CHIP_TYPE_SCHIZO 3
#define PBM_CHIP_TYPE_SCHIZO_PLUS 4
#define PBM_CHIP_TYPE_TOMATILLO 5
int chip_version;
int chip_revision;
/* Name used for top-level resources. */
char *name;
/* OBP specific information. */
struct device_node *prom_node;
u64 ino_bitmap;
/* PBM I/O and Memory space resources. */
struct resource io_space;
struct resource mem_space;
/* Base of PCI Config space, can be per-PBM or shared. */
unsigned long config_space;
/* State of 66MHz capabilities on this PBM. */
int is_66mhz_capable;
int all_devs_66mhz;
#ifdef CONFIG_PCI_MSI
/* MSI info. */
u32 msiq_num;
u32 msiq_ent_count;
u32 msiq_first;
u32 msiq_first_devino;
u32 msi_num;
u32 msi_first;
u32 msi_data_mask;
u32 msix_data_width;
u64 msi32_start;
u64 msi64_start;
u32 msi32_len;
u32 msi64_len;
void *msi_queues;
unsigned long *msi_bitmap;
int (*setup_msi_irq)(unsigned int *virt_irq_p, struct pci_dev *pdev,
struct msi_desc *entry);
void (*teardown_msi_irq)(unsigned int virt_irq, struct pci_dev *pdev);
#endif /* !(CONFIG_PCI_MSI) */
/* This PBM's streaming buffer. */
struct strbuf stc;
/* IOMMU state, potentially shared by both PBM segments. */
struct iommu *iommu;
/* Now things for the actual PCI bus probes. */
unsigned int pci_first_busno;
unsigned int pci_last_busno;
struct pci_bus *pci_bus;
void (*scan_bus)(struct pci_pbm_info *);
struct pci_ops *pci_ops;
};
struct pci_controller_info {
/* The PCI bus modules controlled by us. */
struct pci_pbm_info pbm_A;
struct pci_pbm_info pbm_B;
};
extern struct pci_pbm_info *pci_pbm_root;
extern unsigned long pci_memspace_mask;
extern int pci_num_controllers;
extern int pci_num_pbms;
/* PCI bus scanning and fixup support. */
extern void pci_iommu_table_init(struct iommu *iommu, int tsbsize,
u32 dma_offset, u32 dma_addr_mask);
extern void pci_get_pbm_props(struct pci_pbm_info *pbm);
extern struct pci_bus *pci_scan_one_pbm(struct pci_pbm_info *pbm);
extern void pci_determine_mem_io_space(struct pci_pbm_info *pbm);
......@@ -30,9 +144,9 @@ extern int pci_host_bridge_write_pci_cfg(struct pci_bus *bus_dev,
u32 value);
/* Error reporting support. */
extern void pci_scan_for_target_abort(struct pci_controller_info *, struct pci_pbm_info *, struct pci_bus *);
extern void pci_scan_for_master_abort(struct pci_controller_info *, struct pci_pbm_info *, struct pci_bus *);
extern void pci_scan_for_parity_error(struct pci_controller_info *, struct pci_pbm_info *, struct pci_bus *);
extern void pci_scan_for_target_abort(struct pci_pbm_info *, struct pci_bus *);
extern void pci_scan_for_master_abort(struct pci_pbm_info *, struct pci_bus *);
extern void pci_scan_for_parity_error(struct pci_pbm_info *, struct pci_bus *);
/* Configuration space access. */
extern void pci_config_read8(u8 *addr, u8 *ret);
......
......@@ -8,10 +8,12 @@
#include <linux/sched.h>
#include <linux/mm.h>
#include <linux/delay.h>
#include <linux/pci.h>
#include <asm/pbm.h>
#include <asm/oplib.h>
#include "iommu_common.h"
#include "pci_impl.h"
#define PCI_STC_CTXMATCH_ADDR(STC, CTX) \
((STC)->strbuf_ctxmatch_base + ((CTX) << 3))
......
This diff is collapsed.
......@@ -13,12 +13,12 @@
#include <linux/interrupt.h>
#include <asm/apb.h>
#include <asm/pbm.h>
#include <asm/iommu.h>
#include <asm/irq.h>
#include <asm/smp.h>
#include <asm/oplib.h>
#include <asm/prom.h>
#include <asm/of_device.h>
#include "pci_impl.h"
#include "iommu_common.h"
......@@ -494,11 +494,11 @@ static struct pci_ops sabre_ops = {
};
/* SABRE error handling support. */
static void sabre_check_iommu_error(struct pci_controller_info *p,
static void sabre_check_iommu_error(struct pci_pbm_info *pbm,
unsigned long afsr,
unsigned long afar)
{
struct iommu *iommu = p->pbm_A.iommu;
struct iommu *iommu = pbm->iommu;
unsigned long iommu_tag[16];
unsigned long iommu_data[16];
unsigned long flags;
......@@ -526,8 +526,8 @@ static void sabre_check_iommu_error(struct pci_controller_info *p,
type_string = "Unknown";
break;
};
printk("SABRE%d: IOMMU Error, type[%s]\n",
p->index, type_string);
printk("%s: IOMMU Error, type[%s]\n",
pbm->name, type_string);
/* Enter diagnostic mode and probe for error'd
* entries in the IOTLB.
......@@ -536,7 +536,7 @@ static void sabre_check_iommu_error(struct pci_controller_info *p,
sabre_write(iommu->iommu_control,
(control | SABRE_IOMMUCTRL_DENAB));
for (i = 0; i < 16; i++) {
unsigned long base = p->pbm_A.controller_regs;
unsigned long base = pbm->controller_regs;
iommu_tag[i] =
sabre_read(base + SABRE_IOMMU_TAG + (i * 8UL));
......@@ -566,13 +566,13 @@ static void sabre_check_iommu_error(struct pci_controller_info *p,
type_string = "Unknown";
break;
};
printk("SABRE%d: IOMMU TAG(%d)[RAW(%016lx)error(%s)wr(%d)sz(%dK)vpg(%08lx)]\n",
p->index, i, tag, type_string,
printk("%s: IOMMU TAG(%d)[RAW(%016lx)error(%s)wr(%d)sz(%dK)vpg(%08lx)]\n",
pbm->name, i, tag, type_string,
((tag & SABRE_IOMMUTAG_WRITE) ? 1 : 0),