• Lennert Buytenhek's avatar
    dsa: add switch chip cascading support · e84665c9
    Lennert Buytenhek authored
    The initial version of the DSA driver only supported a single switch
    chip per network interface, while DSA-capable switch chips can be
    interconnected to form a tree of switch chips.  This patch adds support
    for multiple switch chips on a network interface.
    An example topology for a 16-port device with an embedded CPU is as
    	+-----+          +--------+       +--------+
    	|     |eth0    10| switch |9    10| switch |
    	| CPU +----------+        +-------+        |
    	|     |          | chip 0 |       | chip 1 |
    	+-----+          +---++---+       +---++---+
    	                     ||               ||
    	                     ||               ||
    	                     ||1000baseT      ||1000baseT
    	                     ||ports 1-8      ||ports 9-16
    This requires a couple of interdependent changes in the DSA layer:
    - The dsa platform driver data needs to be extended: there is still
      only one netdevice per DSA driver instance (eth0 in the example
      above), but each of the switch chips in the tree needs its own
      mii_bus device pointer, MII management bus address, and port name
      array. (include/net/dsa.h)  The existing in-tree dsa users need
      some small changes to deal with this. (arch/arm)
    - The DSA and Ethertype DSA tagging modules need to be extended to
      use the DSA device ID field on receive and demultiplex the packet
      accordingly, and fill in the DSA device ID field on transmit
      according to which switch chip the packet is heading to.
    - The concept of "CPU port", which is the switch chip port that the
      CPU is connected to (port 10 on switch chip 0 in the example), needs
      to be extended with the concept of "upstream port", which is the
      port on the switch chip that will bring us one hop closer to the CPU
      (port 10 for both switch chips in the example above).
    - The dsa platform data needs to specify which ports on which switch
      chips are links to other switch chips, so that we can enable DSA
      tagging mode on them.  (For inter-switch links, we always use
      non-EtherType DSA tagging, since it has lower overhead.  The CPU
      link uses dsa or edsa tagging depending on what the 'root' switch
      chip supports.)  This is done by specifying "dsa" for the given
      port in the port array.
    - The dsa platform data needs to be extended with information on via
      which port to reach any given switch chip from any given switch chip.
      This info is specified via the per-switch chip data struct ->rtable[]
      array, which gives the nexthop ports for each of the other switches
      in the tree.
    For the example topology above, the dsa platform data would look
    something like this:
    	static struct dsa_chip_data sw[2] = {
    			.mii_bus	= &foo,
    			.sw_addr	= 1,
    			.port_names[0]	= "p1",
    			.port_names[1]	= "p2",
    			.port_names[2]	= "p3",
    			.port_names[3]	= "p4",
    			.port_names[4]	= "p5",
    			.port_names[5]	= "p6",
    			.port_names[6]	= "p7",
    			.port_names[7]	= "p8",
    			.port_names[9]	= "dsa",
    			.port_names[10]	= "cpu",
    			.rtable		= (s8 []){ -1, 9, },
    		}, {
    			.mii_bus	= &foo,
    			.sw_addr	= 2,
    			.port_names[0]	= "p9",
    			.port_names[1]	= "p10",
    			.port_names[2]	= "p11",
    			.port_names[3]	= "p12",
    			.port_names[4]	= "p13",
    			.port_names[5]	= "p14",
    			.port_names[6]	= "p15",
    			.port_names[7]	= "p16",
    			.port_names[10]	= "dsa",
    			.rtable		= (s8 []){ 10, -1, },
    	static struct dsa_platform_data pd = {
    		.netdev		= &foo,
    		.nr_switches	= 2,
    		.sw		= sw,
    Signed-off-by: default avatarLennert Buytenhek <buytenh@marvell.com>
    Tested-by: default avatarGary Thomas <gary@mlbassoc.com>
    Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
wrt350n-v2-setup.c 4.67 KB