• Krzysztof Hałasa's avatar
    CNS3xxx: Fix logical PCIe topology. · defaa4d1
    Krzysztof Hałasa authored
    
    
    Without this patch, each root port and the device connected directly to it seem
    to be located on a shared (virtual) bus #0. It creates problems with enabling
    devices (the PCI code doesn't know that the root bridge must be enabled in order
    to access other devices).
    The PCIe topology shown by lspci doesn't reflect reality, e.g.:
    
    0000:00:00.0 PCI bridge: Cavium Networks Device 3400
    0000:00:01.0 PCI bridge: Texas Instruments XIO2001 PCI Express-to-PCI Bridge
    0000:02:...
    0001:00:00.0 PCI bridge: Cavium Networks Device 3400 (for the second lane/bus)
    
    -+-[0001:00]---00.0-[01]--
     \-[0000:00]-+-00.0-[01]--
                 | ^^^^ root bridge
                 \-01.0-[02]----...
                   ^^^^ first external device
    
    With this patch, the first external PCIe device is connected to bus #1
    (behind the root bridge).
    
    -+-[0001:00]---00.0-[01]--
     \-[0000:00]---00.0-[01-02]----------00.0-[02]----...
                   ^^^^ root bridge      ^^^^ first external device
    Signed-off-by: default avatarKrzysztof Hałasa <khalasa@piap.pl>
    Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
    defaa4d1
pcie.c 9.2 KB