• Chris Wilson's avatar
    drm/i915: Actually invalidate the TLB for the SandyBridge HW contexts w/a · ac82ea2e
    Chris Wilson authored
    A side-effect of commit 7d54a904
    
    
    Author: Chris Wilson <chris@chris-wilson.co.uk>
    Date:   Fri Aug 10 10:18:10 2012 +0100
    
        drm/i915: Apply post-sync write for pipe control invalidates
    
    was that only a request to emit invalidate flush would result in the
    TLB being invalidated (since it requires synchronisation and so incurs a
    performance penalty). However, the stated w/a for hardware contexts is
    that the TLBs must be invalidated prior to a MI_SET_CONTEXT, yet the w/a
    itself did not request the TLBs to be invalidated...
    
    Note this w/a does not prevent the hard system hang I experience when
    using hw contexts (with rc6 enabled) on SNB GT1.
    Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
    Cc: Ben Widawsky <ben@bwidawsk.net>
    Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
    ac82ea2e
i915_gem_context.c 16 KB