• Will Deacon's avatar
    ARM: 7291/1: cache: assume 64-byte L1 cachelines for ARMv7 CPUs · a092f2b1
    Will Deacon authored
    To ensure correct alignment of cacheline-aligned data, the maximum
    cacheline size needs to be known at compile time.
    Since Cortex-A8 and Cortex-A15 have 64-byte cachelines (and it is likely
    that there will be future ARMv7 implementations with the same line size)
    then it makes sense to assume that CPU_V7 implies a 64-byte L1 cacheline
    size. For CPUs with smaller caches, this will result in some harmless
    padding but will help with single zImage work and avoid hitting subtle
    bugs with misaligned data structures.
    Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
    Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
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