• Russell King's avatar
    [ARM] nommu: provide a way for correct control register value selection · 22b19086
    Russell King authored
    Most MMU-based CPUs have a restriction on the setting of the data cache
    enable and mmu enable bits in the control register, whereby if the data
    cache is enabled, the MMU must also be enabled.  Enabling the data
    cache without the MMU is an invalid combination.
    However, there are CPUs where the data cache can be enabled without the
    In order to allow these CPUs to take advantage of that, provide a
    method whereby each proc-*.S file defines the control regsiter value
    for use with nommu (with the MMU disabled.)  Later on, when we add
    support for enabling the MMU on these devices, we can adjust the
    "crval" macro to also enable the data cache for nommu.
    Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
proc-arm1020.S 13 KB