• Ben Widawsky's avatar
    drm/i915: rc6 in sysfs · 0136db58
    Ben Widawsky authored
    Merge rc6 information into the power group for our device. Until now the
    i915 driver has not had any sysfs entries (aside from the connector
    stuff enabled by drm core). Since it seems like we're likely to have
    more in the future I created a new file for sysfs stubs, as well as the
    rc6 sysfs functions which don't really belong elsewhere (perhaps
    i915_suspend, but most of the stuff is in intel_display,c).
    displays rc6 modes enabled (as a hex mask):
    cat /sys/class/drm/card0/power/rc6_enable
    displays #ms GPU has been in rc6 since boot:
    cat /sys/class/drm/card0/power/rc6_residency_ms
    displays #ms GPU has been in deep rc6 since boot:
    cat /sys/class/drm/card0/power/rc6p_residency_ms
    displays #ms GPU has been in deepest rc6 since boot:
    cat /sys/class/drm/card0/power/rc6pp_residency_ms
    Important note: I've seen on SNB that even when RC6 is *not* enabled the
    rc6 register seems to have a random value in it. I can only guess at the
    reason reason for this. Those writing tools that utilize this value need
    to be careful and probably want to scrutinize the value very carefully.
    v2: use common rc6 residency units to milliseconds for the other RC6 types
    v3: don't create sysfs files for GEN <= 5
    add a rc6_enable to show a mask of enabled rc6 types
    use unmerge instead of remove for sysfs group
    squash intel_enable_rc6() extraction into this patch
    v4: rename sysfs files (Chris)
    CC: Chris Wilson <chris@chris-wilson.co.uk>
    CC: Daniel Vetter <daniel.vetter@ffwll.ch>f
    CC: Arjan van de Ven <arjan@linux.intel.com>
    Signed-off-by: default avatarBen Widawsky <benjamin.widawsky@intel.com>
    Reviewed-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
    [danvet: squash in the 64bit division fix by Chris Wilson.]
    Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>