1. 26 Nov, 2014 1 commit
  2. 25 Nov, 2014 2 commits
  3. 24 Nov, 2014 15 commits
    • Peter Maydell's avatar
      Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into staging · ca602818
      Peter Maydell authored
      pc, pci, misc bugfixes
      
      A bunch of bugfixes for 2.2.
      Signed-off-by: 's avatarMichael S. Tsirkin <mst@redhat.com>
      
      # gpg: Signature made Mon 24 Nov 2014 18:59:47 GMT using RSA key ID D28D5469
      # gpg: Good signature from "Michael S. Tsirkin <mst@kernel.org>"
      # gpg:                 aka "Michael S. Tsirkin <mst@redhat.com>"
      
      * remotes/mst/tags/for_upstream:
        pc: acpi: mark all possible CPUs as enabled in SRAT
        pcie: fix improper use of negative value
        pcie: fix typo in pcie_cap_deverr_init()
        target-i386: move generic memory hotplug methods to DSDTs
        acpi-build: mark RAM dirty on table update
        hw/pci: fix crash on shpc error flow
        pc: count in 1Gb hugepage alignment when sizing hotplug-memory container
        pc: explicitly check maxmem limit when adding DIMM
        pc: pc-dimm: use backend alignment during address auto allocation
        pc: align DIMM's address/size by backend's alignment value
        memory: expose alignment used for allocating RAM as MemoryRegion API
        pc: limit DIMM address and size to page aligned values
        pc: make pc_dimm_plug() more readble
        pc: kvm: check if KVM has free memory slots to avoid abort()
        qemu-char: fix tcp_get_fds
      Signed-off-by: 's avatarPeter Maydell <peter.maydell@linaro.org>
      ca602818
    • Igor Mammedov's avatar
      pc: acpi: mark all possible CPUs as enabled in SRAT · dd0247e0
      Igor Mammedov authored
      If QEMU is started with  -numa ... Windows only notices that
      CPU has been hot-added but it will not online such CPUs.
      
      It's caused by the fact that possible CPUs are flagged as
      not enabled in SRAT and Windows honoring that information
      doesn't use corresponding CPU.
      
      ACPI 5.0 Spec regarding to flag says:
      "
      Table 5-47 Local APIC Flags
      ...
      Enabled: if zero, this processor is unusable, and the operating system
      support will not attempt to use it.
      "
      
      Fix QEMU to adhere to spec and mark possible CPUs as enabled
      in SRAT.
      
      With that Windows onlines hot-added CPUs as expected.
      Signed-off-by: 's avatarIgor Mammedov <imammedo@redhat.com>
      Reviewed-by: 's avatarMichael S. Tsirkin <mst@redhat.com>
      Signed-off-by: 's avatarMichael S. Tsirkin <mst@redhat.com>
      dd0247e0
    • Gonglei's avatar
      6c150fbd
    • Gonglei's avatar
    • Paolo Bonzini's avatar
      target-i386: move generic memory hotplug methods to DSDTs · 4f99ab7a
      Paolo Bonzini authored
      This makes it simpler to keep the SSDT byte-for-byte identical for a
      given machine type, which is a goal we want to have for 2.2 and newer
      types.
      Signed-off-by: 's avatarPaolo Bonzini <pbonzini@redhat.com>
      Reviewed-by: 's avatarMichael S. Tsirkin <mst@redhat.com>
      Signed-off-by: 's avatarMichael S. Tsirkin <mst@redhat.com>
      4f99ab7a
    • Michael S. Tsirkin's avatar
      acpi-build: mark RAM dirty on table update · ad5b88b1
      Michael S. Tsirkin authored
      acpi build modifies internal FW CFG RAM on first access
      but we forgot to mark it dirty.
      If this RAM has been migrated already, it won't be
      migrated again, returning corrupted tables to guest.
      Signed-off-by: 's avatarMichael S. Tsirkin <mst@redhat.com>
      ad5b88b1
    • Marcel Apfelbaum's avatar
      hw/pci: fix crash on shpc error flow · 109e90e4
      Marcel Apfelbaum authored
      If the pci bridge enters in error flow as part
      of init process it will only delete the shpc mmio
      subregion but not remove it from the properties list,
      resulting in segmentation fault when the bridge runs
      the exit function.
      
      Example: add a pci bridge without specifing the chassis number:
          <qemu-bin> ... -device pci-bridge,id=p1
      Result:
          (qemu) qemu-system-x86_64: -device pci-bridge,id=p1: Bridge chassis not specified. Each bridge is required to be assigned a unique chassis id > 0.
          qemu-system-x86_64: -device pci-bridge,id=p1: Device
          initialization failed.
          Segmentation fault (core dumped)
      
          if (child->class->unparent) {
          #0  0x00005555558d629b in object_finalize_child_property (obj=0x555556d2e830, name=0x555556d30630 "shpc-mmio[0]", opaque=0x555556a42fc8) at qom/object.c:1078
          #1  0x00005555558d4b1f in object_property_del_all (obj=0x555556d2e830) at qom/object.c:367
          #2  0x00005555558d4ca1 in object_finalize (data=0x555556d2e830) at qom/object.c:412
          #3  0x00005555558d55a1 in object_unref (obj=0x555556d2e830) at qom/object.c:720
          #4  0x000055555572c907 in qdev_device_add (opts=0x5555563544f0) at qdev-monitor.c:566
          #5  0x0000555555744f16 in device_init_func (opts=0x5555563544f0, opaque=0x0) at vl.c:2213
          #6  0x00005555559cf5f0 in qemu_opts_foreach (list=0x555555e0f8e0 <qemu_device_opts>, func=0x555555744efa <device_init_func>, opaque=0x0, abort_on_failure=1) at util/qemu-option.c:1057
          #7  0x000055555574a11b in main (argc=16, argv=0x7fffffffdde8, envp=0x7fffffffde70) at vl.c:423
      
      Unparent the shpc mmio region as part of shpc cleanup.
      Signed-off-by: 's avatarMarcel Apfelbaum <marcel.a@redhat.com>
      Reviewed-by: 's avatarMichael S. Tsirkin <mst@redhat.com>
      Signed-off-by: 's avatarMichael S. Tsirkin <mst@redhat.com>
      Reviewed-by: 's avatarAmos Kong <akong@redhat.com>
      109e90e4
    • Igor Mammedov's avatar
      pc: count in 1Gb hugepage alignment when sizing hotplug-memory container · 085f8e88
      Igor Mammedov authored
      if DIMMs with different size/alignment are interleaved
      in creation order, it could lead to hotplug-memory
      container fragmentation and following inability to use
      all RAM upto maxmem.
      For example:
          -m 4G,slots=3,maxmem=7G
          -object memory-backend-file,id=mem-1,size=256M,mem-path=/pagesize-2MB
          -device pc-dimm,id=mem1,memdev=mem-1
          -object memory-backend-file,id=mem-2,size=1G,mem-path=/pagesize-1GB
          -device pc-dimm,id=mem2,memdev=mem-2
          -object memory-backend-file,id=mem-3,size=256M,mem-path=/pagesize-2MB
          -device pc-dimm,id=mem3,memdev=mem-3
      
      fragments hotplug-memory container and doesn't allow
      to use 1GB hugepage backend to consume remainig 1Gb.
      
      To ease managment factor count in max 1Gb alignment for
      each memory slot when sizing hotplug-memory region so
      that regadless of fragmentaion it would be possible to
      add max aligned DIMM.
      Signed-off-by: 's avatarIgor Mammedov <imammedo@redhat.com>
      Reviewed-by: 's avatarMichael S. Tsirkin <mst@redhat.com>
      Signed-off-by: 's avatarMichael S. Tsirkin <mst@redhat.com>
      085f8e88
    • Igor Mammedov's avatar
      pc: explicitly check maxmem limit when adding DIMM · b03541fa
      Igor Mammedov authored
      Currently maxmem limit is not checked and depends on
      hotplug region container not being able to fit more RAM
      than maxmem. Do check explicitly so that it would
      be possible to change hotplug container size later
      to deal with fragmentation.
      Signed-off-by: 's avatarIgor Mammedov <imammedo@redhat.com>
      Reviewed-by: 's avatarMichael S. Tsirkin <mst@redhat.com>
      Signed-off-by: 's avatarMichael S. Tsirkin <mst@redhat.com>
      b03541fa
    • Peter Maydell's avatar
      Merge remote-tracking branch 'remotes/kevin/tags/for-upstream' into staging · 3d4a70f8
      Peter Maydell authored
      Block patches for 2.2.0-rc3
      
      # gpg: Signature made Mon 24 Nov 2014 12:52:23 GMT using RSA key ID C88F2FD6
      # gpg: Good signature from "Kevin Wolf <kwolf@redhat.com>"
      
      * remotes/kevin/tags/for-upstream:
        Revert "qemu-img info: show nocow info"
      Signed-off-by: 's avatarPeter Maydell <peter.maydell@linaro.org>
      3d4a70f8
    • Peter Maydell's avatar
      Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into staging · a31a7475
      Peter Maydell authored
      Three patches to fix ExtINT for the QEMU implementation of the local APIC.
      
      # gpg: Signature made Mon 24 Nov 2014 13:38:36 GMT using RSA key ID 78C7AE83
      # gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>"
      # gpg:                 aka "Paolo Bonzini <pbonzini@redhat.com>"
      # gpg: WARNING: This key is not certified with sufficiently trusted signatures!
      # gpg:          It is not certain that the signature belongs to the owner.
      # Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4  E2F7 7E15 100C CD36 69B1
      #      Subkey fingerprint: F133 3857 4B66 2389 866C  7682 BFFB D25F 78C7 AE83
      
      * remotes/bonzini/tags/for-upstream:
        apic: fix incorrect handling of ExtINT interrupts wrt processor priority
        apic: fix loss of IPI due to masked ExtINT
        apic: avoid getting out of halted state on masked PIC interrupts
      Signed-off-by: 's avatarPeter Maydell <peter.maydell@linaro.org>
      a31a7475
    • Paolo Bonzini's avatar
      apic: fix incorrect handling of ExtINT interrupts wrt processor priority · 5224c88d
      Paolo Bonzini authored
      This fixes another failure with ExtINT, demonstrated by QNX.  The failure
      mode is as follows:
      - IPI sent to cpu 0 (bit set in APIC irr)
      - IPI accepted by cpu 0 (bit cleared in irr, set in isr)
      - IPI sent to cpu 0 (bit set in both irr and isr)
      - PIC interrupt sent to cpu 0
      
      The PIC interrupt causes CPU_INTERRUPT_HARD to be set, but
      apic_irq_pending observes that the highest pending APIC interrupt priority
      (the IPI) is the same as the processor priority (since the IPI is still
      being handled), so apic_get_interrupt returns a spurious interrupt rather
      than the pending PIC interrupt. The result is an endless sequence of
      spurious interrupts, since nothing will clear CPU_INTERRUPT_HARD.
      
      Instead, ExtINT interrupts should have ignored the processor priority.
      Calling apic_check_pic early in apic_get_interrupt ensures that
      apic_deliver_pic_intr is called instead of delivering the spurious
      interrupt.  apic_deliver_pic_intr then clears CPU_INTERRUPT_HARD if needed.
      Reported-by: 's avatarRichard Bilson <rbilson@qnx.com>
      Tested-by: 's avatarRichard Bilson <rbilson@qnx.com>
      Signed-off-by: 's avatarPaolo Bonzini <pbonzini@redhat.com>
      5224c88d
    • Paolo Bonzini's avatar
      apic: fix loss of IPI due to masked ExtINT · 8092cb71
      Paolo Bonzini authored
      This patch fixes an obscure failure of the QNX kernel on QEMU x86 SMP.
      In QNX, all hardware interrupts come via the PIC, and are delivered by
      the cpu 0 LAPIC in ExtINT mode, while IPIs are delivered by the LAPIC
      in fixed mode.
      
      This bug happens as follows:
      - cpu 0 masks a particular PIC interrupt
      - IPI sent to cpu 0 (CPU_INTERRUPT_HARD is set)
      - before the IPI is accepted, the masked interrupt line is asserted by the
      device
      
      Since the interrupt is masked, apic_deliver_pic_intr will clear
      CPU_INTERRUPT_HARD. The IPI will still be set in the APIC irr, but since
      CPU_INTERRUPT_HARD is not set the cpu will not notice. Depending on the
      scenario this can cause a system hang, i.e. if cpu 0 is expected to unmask
      the interrupt.
      
      In order to fix this, do a full check of the APIC before an EXTINT
      is acknowledged.  This can result in clearing CPU_INTERRUPT_HARD, but
      can also result in delivering the lost IPI.
      Reported-by: 's avatarRichard Bilson <rbilson@qnx.com>
      Tested-by: 's avatarRichard Bilson <rbilson@qnx.com>
      Signed-off-by: 's avatarPaolo Bonzini <pbonzini@redhat.com>
      8092cb71
    • Paolo Bonzini's avatar
      apic: avoid getting out of halted state on masked PIC interrupts · 60e68042
      Paolo Bonzini authored
      After the next patch, if a masked PIC interrupts causes CPU_INTERRUPT_POLL
      to be set, the CPU will spuriously get out of halted state.  While this
      is technically valid, we should avoid that.
      
      Make CPU_INTERRUPT_POLL run apic_update_irq in the right thread and then
      look at CPU_INTERRUPT_HARD.  If CPU_INTERRUPT_HARD does not get set,
      do not report the CPU as having work.
      
      Also move the handling of software-disabled APIC from apic_update_irq
      to apic_irq_pending, and always trigger CPU_INTERRUPT_POLL.  This will
      be important once we will add a case that resets CPU_INTERRUPT_HARD
      from apic_update_irq.  We want to run it even if we go through
      CPU_INTERRUPT_POLL, and even if the local APIC is software disabled.
      Reported-by: 's avatarRichard Bilson <rbilson@qnx.com>
      Tested-by: 's avatarRichard Bilson <rbilson@qnx.com>
      Signed-off-by: 's avatarPaolo Bonzini <pbonzini@redhat.com>
      60e68042
    • Kevin Wolf's avatar
      Revert "qemu-img info: show nocow info" · 24bf10da
      Kevin Wolf authored
      This reverts commit 000c4dff.
      
      The main reason for reverting this commit before the 2.2 release is that
      it adds a QAPI interface that we don't want to keep: The 'nocow' flag
      doesn't generally make sense for block nodes, but only for the raw-posix
      driver. It should therefore be part of ImageInfoSpecific rather than
      ImageInfo.
      
      The commit contains more problems, but unlike the API stability issue
      they wouldn't justify reverting it.
      
      Conflicts:
      	block/qapi.c
      Signed-off-by: 's avatarKevin Wolf <kwolf@redhat.com>
      Reviewed-by: 's avatarEric Blake <eblake@redhat.com>
      Reviewed-by: 's avatarStefan Hajnoczi <stefanha@redhat.com>
      24bf10da
  4. 23 Nov, 2014 7 commits
  5. 21 Nov, 2014 8 commits
  6. 20 Nov, 2014 7 commits