1. 22 Mar, 2013 1 commit
  2. 03 Mar, 2013 3 commits
  3. 26 Feb, 2013 1 commit
    • Peter Maydell's avatar
      qemu-log: default to stderr for logging output · 989b697d
      Peter Maydell authored
      Switch the default for qemu_log logging output from "/tmp/qemu.log"
      to stderr. This is an incompatible change in some sense, but logging
      is mostly used for debugging purposes so it shouldn't affect production
      use. The previous behaviour can be obtained by adding "-D /tmp/qemu.log"
      to the command line.
      
      This change requires us to:
       * update all the documentation/help text (we take the opportunity
         to smooth out minor inconsistencies between the phrasing in
         linux-user/bsd-user/system help messages)
       * make linux-user and bsd-user defer to qemu-log for the default
         logging destination rather than overriding it themselves
       * ensure that all logfile closing is done via qemu_log_close()
         and that that function doesn't close stderr
      as well as the obvious change to the behaviour of do_qemu_set_log()
      when no logfile name has been specified.
      Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
      Reviewed-by: default avatarStefan Hajnoczi <stefanha@redhat.com>
      Reviewed-by: default avatarMarkus Armbruster <armbru@redhat.com>
      Message-id: 1361901160-28729-1-git-send-email-peter.maydell@linaro.org
      Signed-off-by: default avatarAnthony Liguori <aliguori@us.ibm.com>
      989b697d
  4. 23 Feb, 2013 12 commits
  5. 17 Feb, 2013 1 commit
  6. 16 Feb, 2013 3 commits
  7. 19 Jan, 2013 4 commits
    • Peter Maydell's avatar
      tcg/target-arm: Add missing parens to assertions · 5256a720
      Peter Maydell authored
      Silence a (legitimate) complaint about missing parentheses:
      
      tcg/arm/tcg-target.c: In function ‘tcg_out_qemu_ld’:
      tcg/arm/tcg-target.c:1148:5: error: suggest parentheses around
      comparison in operand of ‘&’ [-Werror=parentheses]
      tcg/arm/tcg-target.c: In function ‘tcg_out_qemu_st’:
      tcg/arm/tcg-target.c:1357:5: error: suggest parentheses around
      comparison in operand of ‘&’ [-Werror=parentheses]
      
      which meant that we would mistakenly always assert if running
      a QEMU built with debug enabled on ARM.
      Signed-off-by: default avatarPeter Maydell <peter.maydelL@linaro.org>
      Signed-off-by: default avatarBlue Swirl <blauwirbel@gmail.com>
      5256a720
    • Paolo Bonzini's avatar
      optimize: optimize using nonzero bits · 633f6502
      Paolo Bonzini authored
      This adds two optimizations using the non-zero bit mask.  In some cases
      involving shifts or ANDs the value can become zero, and can thus be
      optimized to a move of zero.  Second, useless zero-extension or an
      AND with constant can be detected that would only zero bits that are
      already zero.
      
      The main advantage of this optimization is that it turns zero-extensions
      into moves, thus enabling much better copy propagation (around 1% code
      reduction).  Here is for example a "test $0xff0000,%ecx + je" before
      optimization:
      
       mov_i64 tmp0,rcx
       movi_i64 tmp1,$0xff0000
       discard cc_src
       and_i64 cc_dst,tmp0,tmp1
       movi_i32 cc_op,$0x1c
       ext32u_i64 tmp0,cc_dst
       movi_i64 tmp12,$0x0
       brcond_i64 tmp0,tmp12,eq,$0x0
      
      and after (without patch on the left, with on the right):
      
       movi_i64 tmp1,$0xff0000                 movi_i64 tmp1,$0xff0000
       discard cc_src                          discard cc_src
       and_i64 cc_dst,rcx,tmp1                 and_i64 cc_dst,rcx,tmp1
       movi_i32 cc_op,$0x1c                    movi_i32 cc_op,$0x1c
       ext32u_i64 tmp0,cc_dst
       movi_i64 tmp12,$0x0                     movi_i64 tmp12,$0x0
       brcond_i64 tmp0,tmp12,eq,$0x0           brcond_i64 cc_dst,tmp12,eq,$0x0
      
      Other similar cases: "test %eax, %eax + jne" where eax is already 32-bit
      (after optimization, without patch on the left, with on the right):
      
       discard cc_src                          discard cc_src
       mov_i64 cc_dst,rax                      mov_i64 cc_dst,rax
       movi_i32 cc_op,$0x1c                    movi_i32 cc_op,$0x1c
       ext32u_i64 tmp0,cc_dst
       movi_i64 tmp12,$0x0                     movi_i64 tmp12,$0x0
       brcond_i64 tmp0,tmp12,ne,$0x0           brcond_i64 rax,tmp12,ne,$0x0
      
      "test $0x1, %dl + je":
      
       movi_i64 tmp1,$0x1                      movi_i64 tmp1,$0x1
       discard cc_src                          discard cc_src
       and_i64 cc_dst,rdx,tmp1                 and_i64 cc_dst,rdx,tmp1
       movi_i32 cc_op,$0x1a                    movi_i32 cc_op,$0x1a
       ext8u_i64 tmp0,cc_dst
       movi_i64 tmp12,$0x0                     movi_i64 tmp12,$0x0
       brcond_i64 tmp0,tmp12,eq,$0x0           brcond_i64 cc_dst,tmp12,eq,$0x0
      
      In some cases TCG even outsmarts GCC. :)  Here the input code has
      "and $0x2,%eax + movslq %eax,%rbx + test %rbx, %rbx" and the optimizer,
      thanks to copy propagation, does the following:
      
       movi_i64 tmp12,$0x2                     movi_i64 tmp12,$0x2
       and_i64 rax,rax,tmp12                   and_i64 rax,rax,tmp12
       mov_i64 cc_dst,rax                      mov_i64 cc_dst,rax
       ext32s_i64 tmp0,rax                  -> nop
       mov_i64 rbx,tmp0                     -> mov_i64 rbx,cc_dst
       and_i64 cc_dst,rbx,rbx               -> nop
      Signed-off-by: default avatarPaolo Bonzini <pbonzini@redhat.com>
      Signed-off-by: default avatarRichard Henderson <rth@twiddle.net>
      Signed-off-by: default avatarBlue Swirl <blauwirbel@gmail.com>
      633f6502
    • Paolo Bonzini's avatar
      optimize: track nonzero bits of registers · 3a9d8b17
      Paolo Bonzini authored
      Add a "mask" field to the tcg_temp_info struct.  A bit that is zero
      in "mask" will always be zero in the corresponding temporary.
      Zero bits in the mask can be produced from moves of immediates,
      zero-extensions, ANDs with constants, shifts; they can then be
      be propagated by logical operations, shifts, sign-extensions,
      negations, deposit operations, and conditional moves.  Other
      operations will just reset the mask to all-ones, i.e. unknown.
      
      [rth: s/target_ulong/tcg_target_ulong/]
      Signed-off-by: default avatarPaolo Bonzini <pbonzini@redhat.com>
      Signed-off-by: default avatarRichard Henderson <rth@twiddle.net>
      Signed-off-by: default avatarBlue Swirl <blauwirbel@gmail.com>
      3a9d8b17
    • Paolo Bonzini's avatar
      optimize: only write to state when clearing optimizer data · d193a14a
      Paolo Bonzini authored
      The next patch will add to the TCG optimizer a field that should be
      non-zero in the default case.  Thus, replace the memset of the
      temps array with a loop.  Only the state field has to be up-to-date,
      because others are not used except if the state is TCG_TEMP_COPY
      or TCG_TEMP_CONST.
      
      [rth: Extracted the loop to a function.]
      Signed-off-by: default avatarPaolo Bonzini <pbonzini@redhat.com>
      Signed-off-by: default avatarRichard Henderson <rth@twiddle.net>
      Signed-off-by: default avatarBlue Swirl <blauwirbel@gmail.com>
      d193a14a
  8. 12 Jan, 2013 1 commit
  9. 02 Jan, 2013 1 commit
  10. 29 Dec, 2012 3 commits
  11. 19 Dec, 2012 3 commits
  12. 08 Dec, 2012 1 commit
  13. 07 Dec, 2012 1 commit
  14. 24 Nov, 2012 3 commits
    • Aurelien Jarno's avatar
      tcg: mark local temps as MEM in dead_temp() · e5138db5
      Aurelien Jarno authored
      In dead_temp, local temps should always be marked as back to memory,
      even if they have not been allocated (i.e. they are discared before
      cross a basic block).
      
      It fixes the following assertion in target-xtensa:
      
          qemu-system-xtensa: tcg/tcg.c:1665: temp_save: Assertion `s->temps[temp].val_type == 2 || s->temps[temp].fixed_reg' failed.
          Aborted
      Reported-by: default avatarMax Filippov <jcmvbkbc@gmail.com>
      Tested-by: default avatarMax Filippov <jcmvbkbc@gmail.com>
      Signed-off-by: default avatarAurelien Jarno <aurelien@aurel32.net>
      e5138db5
    • Aurelien Jarno's avatar
      tcg/arm: fix cross-endian qemu_st16 · 7aab08aa
      Aurelien Jarno authored
      The bswap16 TCG opcode assumes that the high bytes of the temp equal
      to 0 before calling it. The ARM backend implementation takes this
      assumption to slightly optimize the generated code.
      
      The same implementation is called for implementing the cross-endian
      qemu_st16 opcode, where this assumption is not true anymore. One way to
      fix that would be to zero the high bytes before calling it. Given the
      store instruction just ignore them, it is possible to provide a slightly
      more optimized version. With ARMv6+ the rev16 instruction does the work
      correctly. For lower ARM versions the patch provides a version which
      behaves correctly with non-zero high bytes, but fill them with junk.
      
      Cc: Andrzej Zaborowski <balrogg@gmail.com>
      Cc: Peter Maydell <peter.maydell@linaro.org>
      Cc: qemu-stable@nongnu.org
      Reviewed-by: default avatarPeter Maydell <peter.maydell@linaro.org>
      Signed-off-by: default avatarAurelien Jarno <aurelien@aurel32.net>
      7aab08aa
    • Aurelien Jarno's avatar
      tcg/arm: fix TLB access in qemu-ld/st ops · d17bd1d8
      Aurelien Jarno authored
      The TCG arm backend considers likely that the offset to the TLB
      entries does not exceed 12 bits for mem_index = 0. In practice this is
      not true for at least the MIPS target.
      
      The current patch fixes that by loading the bits 23-12 with a separate
      instruction, and using loads with address writeback, independently of
      the value of mem_idx. In total this allow a 24-bit offset, which is a
      lot more than needed.
      
      Cc: Andrzej Zaborowski <balrogg@gmail.com>
      Cc: Peter Maydell <peter.maydell@linaro.org>
      Cc: qemu-stable@nongnu.org
      Signed-off-by: default avatarAurelien Jarno <aurelien@aurel32.net>
      d17bd1d8
  15. 20 Nov, 2012 1 commit
  16. 19 Nov, 2012 1 commit