1. 19 Dec, 2012 3 commits
  2. 30 Oct, 2012 1 commit
  3. 05 Oct, 2012 1 commit
  4. 27 Aug, 2012 1 commit
  5. 23 Aug, 2012 1 commit
  6. 11 Aug, 2012 1 commit
  7. 27 Jul, 2012 2 commits
  8. 10 Jul, 2012 1 commit
    • Jan Kiszka's avatar
      apic: Defer interrupt updates to VCPU thread · 5d62c43a
      Jan Kiszka authored
      KVM performs TPR raising asynchronously to QEMU, specifically outside
      QEMU's global lock. When an interrupt is injected into the APIC and TPR
      is checked to decide if this can be delivered, a stale TPR value may be
      used, causing spurious interrupts in the end.
      Fix this by deferring apic_update_irq to the context of the target VCPU.
      We introduce a new interrupt flag for this, CPU_INTERRUPT_POLL. When it
      is set, the VCPU calls apic_poll_irq before checking for further pending
      interrupts. To avoid special-casing KVM, we also implement this logic
      for TCG mode.
      Signed-off-by: default avatarJan Kiszka <jan.kiszka@siemens.com>
      Signed-off-by: default avatarAvi Kivity <avi@redhat.com>
  9. 28 Jun, 2012 1 commit
    • Blue Swirl's avatar
      x86: avoid AREG0 for exceptions · 77b2bc2c
      Blue Swirl authored
      Add an explicit CPUX86State parameter instead of relying on AREG0.
      Merge raise_exception_env() to raise_exception(), likewise with
      raise_exception_err_env() and raise_exception_err().
      Introduce cpu_svm_check_intercept_param() and cpu_vmexit()
      as wrappers.
      Signed-off-by: default avatarBlue Swirl <blauwirbel@gmail.com>
  10. 25 Jun, 2012 1 commit
  11. 15 Jun, 2012 1 commit
  12. 04 Jun, 2012 2 commits
  13. 15 Apr, 2012 1 commit
  14. 30 Mar, 2012 1 commit
    • Anthony Liguori's avatar
      qtest: add test framework · c7f0f3b1
      Anthony Liguori authored
      The idea behind qtest is pretty simple.  Instead of executing a CPU via TCG or
      KVM, rely on an external process to send events to the device model that the CPU
      would normally generate.
      qtest presents itself as an accelerator.  In addition, a new option is added to
      establish a qtest server (-qtest) that takes a character device.  This is what
      allows the external process to send CPU events to the device model.
      qtest uses a simple line based protocol to send the events.  Documentation of
      that protocol is in qtest.c.
      I considered reusing the monitor for this job.  Adding interrupts would be a bit
      difficult.  In addition, logging would also be difficult.
      qtest has extensive logging support.  All protocol commands are logged with
      time stamps using a new command line option (-qtest-log).  Logging is important
      since ultimately, this is a feature for debugging.
      Signed-off-by: default avatarAnthony Liguori <aliguori@us.ibm.com>
      Signed-off-by: default avatarPaolo Bonzini <pbonzini@redhat.com>
      Signed-off-by: default avatarAnthony Liguori <aliguori@us.ibm.com>
  15. 17 Mar, 2012 1 commit
    • Stefan Weil's avatar
      w64: Fix data type of next_tb and tcg_qemu_tb_exec · 69784eae
      Stefan Weil authored
      next_tb is the numeric value of a tcg target (= QEMU host) address.
      Using tcg_target_ulong instead of unsigned long shows this and makes
      the code portable for hosts with an unusual size of long (w64).
      The type cast '(long)(next_tb & ~3)' was not needed (casting
      unsigned long to long does not change the bits, and nor does
      casting long to pointer for most (= all non w64) hosts.
      It is removed here.
      Macro or function tcg_qemu_tb_exec is used to set next_tb.
      The function also returns next_tb. Therefore tcg_qemu_tb_exec
      must return a tcg_target_ulong.
      Signed-off-by: default avatarStefan Weil <sw@weilnetz.de>
      Signed-off-by: default avatarBlue Swirl <blauwirbel@gmail.com>
  16. 14 Mar, 2012 3 commits
  17. 10 Feb, 2012 1 commit
  18. 06 Oct, 2011 1 commit
    • Elie Richa's avatar
      PPC: Fix sync instructions problem in SMP · 4e85f82c
      Elie Richa authored
      In the current emulation of the load-and-reserve (lwarx) and
      store-conditional (stwcx.) instructions, the internal reservation
      mechanism is taken into account, however each CPU has its own
      reservation information and this information is not synchronized between
      CPUs to perform proper synchronization.
      The following test case with 2 CPUs shows that the semantics of the
      "lwarx" and "stwcx." instructions are not preserved by the emulation.
      The test case does the following :
      	- CPU0: reserve a memory location
      	- CPU1: reserve the same memory location
      	- CPU0: perform stwcx. on the location
      The last store-conditional operation succeeds while it is supposed to
      fail since the reservation was supposed to be lost at the second reserve
      This (one line) patch fixes this problem in a very simple manner by
      removing the reservation of a CPU every time it is scheduled (in
      cpu_exec()). While this is a harsh workaround, it does not affect the
      guest code much because reservations are usually held for a very short
      time, that is an lwarx is almost always followed by an stwcx. a few
      instructions below. Therefore, in most cases, the reservation will be
      taken and consumed before a CPU switch occurs. However in the rare case
      where a CPU switch does occur between the lwarx and its corresponding
      stwcx.  this patch solves a potential erroneous behavior of the
      synchronization instructions.
      Signed-off-by: default avatarElie Richa <richa@adacore.com>
      Signed-off-by: default avatarAlexander Graf <agraf@suse.de>
  19. 10 Sep, 2011 3 commits
  20. 12 Jul, 2011 1 commit
  21. 26 Jun, 2011 6 commits
  22. 20 Jun, 2011 1 commit
  23. 31 May, 2011 1 commit
  24. 28 May, 2011 2 commits
  25. 22 May, 2011 1 commit
  26. 08 May, 2011 1 commit