1. 03 Nov, 2014 2 commits
  2. 12 Sep, 2014 1 commit
  3. 22 Aug, 2014 1 commit
  4. 08 Jul, 2014 1 commit
  5. 24 Jun, 2014 1 commit
  6. 23 Jun, 2014 2 commits
  7. 16 Jun, 2014 2 commits
  8. 21 May, 2014 1 commit
  9. 13 May, 2014 1 commit
  10. 02 May, 2014 1 commit
    • Riku Voipio's avatar
      linux-user: remove configure option for setting uname release · e586822a
      Riku Voipio authored
      --enable-uname-release was a rather heavyweight hammer, as it allows
      providing values less that UNAME_MINIMUM_RELEASE. Also, it affects
      all built linux-user targets, which in most cases is not what user
      wants.
      
      Now that we have UNAME_MINIMUM_RELEASE for all linux-user platforms,
      we can drop --enable-uname-release and the related CONFIG_UNAME_RELEASE
      define.
      
      Users can still override the variable with QEMU_UNAME=2.6.32 or -r
      command line option. If distributors need to update a minimum version
      for a specific target, it can be done by updating UNAME_MINIMUM_RELEASE.
      Signed-off-by: default avatarRiku Voipio <riku.voipio@linaro.org>
      e586822a
  11. 17 Apr, 2014 1 commit
    • Peter Maydell's avatar
      target-arm: Define exception record for AArch64 exceptions · abf1172f
      Peter Maydell authored
      For AArch32 exceptions, the only information provided about
      the cause of an exception is the individual exception type (data
      abort, undef, etc), which we store in cs->exception_index. For
      AArch64, the CPU provides much more detail about the cause of
      the exception, which can be found in the syndrome register.
      Create a set of fields in CPUARMState which must be filled in
      whenever an exception is raised, so that exception entry can
      correctly fill in the syndrome register for the guest.
      This includes the information which in AArch32 appears in
      the DFAR and IFAR (fault address registers) and the DFSR
      and IFSR (fault status registers) for data aborts and
      prefetch aborts, since if we end up taking the MMU fault
      to AArch64 rather than AArch32 this will need to end up
      in different system registers.
      
      This patch does a refactoring which moves the setting of the
      AArch32 DFAR/DFSR/IFAR/IFSR from the point where the exception
      is raised to the point where it is taken. (This is no change
      for cores with an MMU, retains the existing clearly incorrect
      behaviour for ARM946 of trashing the MP access permissions
      registers which share the c5_data and c5_insn state fields,
      and has no effect for v7M because we don't implement its
      MPU fault status or address registers.)
      
      As a side effect of the cleanup we fix a bug in the AArch64
      linux-user mode code where we were passing a 64 bit fault
      address through the 32 bit c6_data/c6_insn fields: it now
      goes via the always-64-bit exception.vaddress.
      Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
      Reviewed-by: default avatarPeter Crosthwaite <peter.crosthwaite@xilinx.com>
      abf1172f
  12. 13 Mar, 2014 6 commits
  13. 04 Mar, 2014 1 commit
  14. 03 Mar, 2014 1 commit
  15. 20 Feb, 2014 1 commit
  16. 08 Jan, 2014 2 commits
    • Michael Matz's avatar
      target-arm: A64: support for ld/st/cl exclusive · fa2ef212
      Michael Matz authored
      This implement exclusive loads/stores for aarch64 along the lines of
      arm32 and ppc implementations. The exclusive load remembers the address
      and loaded value. The exclusive store throws an an exception which uses
      those values to check for equality in a proper exclusive region.
      
      This is not actually the architecture mandated semantics (for either
      AArch32 or AArch64) but it is close enough for typical guest code
      sequences to work correctly, and saves us from having to monitor all
      guest stores. It's fairly easy to come up with test cases where we
      don't behave like hardware - we don't for example model cache line
      behaviour. However in the common patterns this works, and the existing
      32 bit ARM exclusive access implementation has the same limitations.
      
      AArch64 also implements new acquire/release loads/stores (which may be
      either exclusive or non-exclusive). These imposes extra ordering
      constraints on memory operations (ie they act as if they have an implicit
      barrier built into them). As TCG is single-threaded all our barriers
      are no-ops, so these just behave like normal loads and stores.
      Signed-off-by: default avatarMichael Matz <matz@suse.de>
      Signed-off-by: default avatarAlex Bennée <alex.bennee@linaro.org>
      Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
      Reviewed-by: default avatarRichard Henderson <rth@twiddle.net>
      fa2ef212
    • Peter Maydell's avatar
      target-arm: Widen exclusive-access support struct fields to 64 bits · 03d05e2d
      Peter Maydell authored
      In preparation for adding support for A64 load/store exclusive instructions,
      widen the fields in the CPU state struct that deal with address and data values
      for exclusives from 32 to 64 bits. Although in practice AArch64 and AArch32
      exclusive accesses will be generally separate there are some odd theoretical
      corner cases (eg you should be able to do the exclusive load in AArch32, take
      an exception to AArch64 and successfully do the store exclusive there), and it's
      also easier to reason about.
      
      The changes in semantics for the variables are:
       exclusive_addr  -> extended to 64 bits; -1ULL for "monitor lost",
         otherwise always < 2^32 for AArch32
       exclusive_val   -> extended to 64 bits. 64 bit exclusives in AArch32 now
         use the high half of exclusive_val instead of a separate exclusive_high
       exclusive_high  -> is no longer used in AArch32; extended to 64 bits as
         it will be needed for AArch64's pair-of-64-bit-values exclusives.
       exclusive_test  -> extended to 64 bits, as it is an address. Since this is
         a linux-user-only field, in arm-linux-user it will always have the top
         32 bits zero.
       exclusive_info  -> stays 32 bits, as it is neither data nor address, but
         simply holds register indexes etc. AArch64 will be able to fit all its
         information into 32 bits as well.
      
      Note that the refactoring of gen_store_exclusive() coincidentally fixes
      a minor bug where ldrexd would incorrectly update the first CPU register
      even if the load for the second register faulted.
      Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
      Reviewed-by: default avatarRichard Henderson <rth@twiddle.net>
      03d05e2d
  17. 07 Jan, 2014 4 commits
    • Michael Matz's avatar
      target-arm: A64: support for ld/st/cl exclusive · 2df75664
      Michael Matz authored
      This implement exclusive loads/stores for aarch64 along the lines of
      arm32 and ppc implementations. The exclusive load remembers the address
      and loaded value. The exclusive store throws an an exception which uses
      those values to check for equality in a proper exclusive region.
      
      This is not actually the architecture mandated semantics (for either
      AArch32 or AArch64) but it is close enough for typical guest code
      sequences to work correctly, and saves us from having to monitor all
      guest stores. It's fairly easy to come up with test cases where we
      don't behave like hardware - we don't for example model cache line
      behaviour. However in the common patterns this works, and the existing
      32 bit ARM exclusive access implementation has the same limitations.
      
      AArch64 also implements new acquire/release loads/stores (which may be
      either exclusive or non-exclusive). These imposes extra ordering
      constraints on memory operations (ie they act as if they have an implicit
      barrier built into them). As TCG is single-threaded all our barriers
      are no-ops, so these just behave like normal loads and stores.
      Signed-off-by: default avatarMichael Matz <matz@suse.de>
      Signed-off-by: default avatarAlex Bennée <alex.bennee@linaro.org>
      Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
      Reviewed-by: default avatarRichard Henderson <rth@twiddle.net>
      2df75664
    • Peter Maydell's avatar
      target-arm: Widen exclusive-access support struct fields to 64 bits · 90ba562c
      Peter Maydell authored
      In preparation for adding support for A64 load/store exclusive instructions,
      widen the fields in the CPU state struct that deal with address and data values
      for exclusives from 32 to 64 bits. Although in practice AArch64 and AArch32
      exclusive accesses will be generally separate there are some odd theoretical
      corner cases (eg you should be able to do the exclusive load in AArch32, take
      an exception to AArch64 and successfully do the store exclusive there), and it's
      also easier to reason about.
      
      The changes in semantics for the variables are:
       exclusive_addr  -> extended to 64 bits; -1ULL for "monitor lost",
         otherwise always < 2^32 for AArch32
       exclusive_val   -> extended to 64 bits. 64 bit exclusives in AArch32 now
         use the high half of exclusive_val instead of a separate exclusive_high
       exclusive_high  -> is no longer used in AArch32; extended to 64 bits as
         it will be needed for AArch64's pair-of-64-bit-values exclusives.
       exclusive_test  -> extended to 64 bits, as it is an address. Since this is
         a linux-user-only field, in arm-linux-user it will always have the top
         32 bits zero.
       exclusive_info  -> stays 32 bits, as it is neither data nor address, but
         simply holds register indexes etc. AArch64 will be able to fit all its
         information into 32 bits as well.
      
      Note that the refactoring of gen_store_exclusive() coincidentally fixes
      a minor bug where ldrexd would incorrectly update the first CPU register
      even if the load for the second register faulted.
      Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
      Reviewed-by: default avatarRichard Henderson <rth@twiddle.net>
      90ba562c
    • Peter Maydell's avatar
      target-arm: Widen thread-local register state fields to 64 bits · e4fe830b
      Peter Maydell authored
      The common pattern for system registers in a 64-bit capable ARM
      CPU is that when in AArch32 the cp15 register is a view of the
      bottom 32 bits of the 64-bit AArch64 system register; writes in
      AArch32 leave the top half unchanged. The most natural way to
      model this is to have the state field in the CPU struct be a
      64 bit value, and simply have the AArch32 TCG code operate on
      a pointer to its lower half.
      
      For aarch64-linux-user the only registers we need to share like
      this are the thread-local-storage ones. Widen their fields to
      64 bits and provide the 64 bit reginfo struct to make them
      visible in AArch64 state. Note that minor cleanup of the AArch64
      system register encoding space means We can share the TPIDR_EL1
      reginfo but need split encodings for TPIDR_EL0 and TPIDRRO_EL0.
      
      Since we're touching almost every line in QEMU that uses the
      c13_tls* fields in this patch anyway, we take the opportunity
      to rename them in line with the standard ARM architectural names
      for these registers.
      Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
      Reviewed-by: default avatarRichard Henderson <rth@twiddle.net>
      e4fe830b
    • Peter Maydell's avatar
      target-arm: Widen thread-local register state fields to 64 bits · 19917791
      Peter Maydell authored
      The common pattern for system registers in a 64-bit capable ARM
      CPU is that when in AArch32 the cp15 register is a view of the
      bottom 32 bits of the 64-bit AArch64 system register; writes in
      AArch32 leave the top half unchanged. The most natural way to
      model this is to have the state field in the CPU struct be a
      64 bit value, and simply have the AArch32 TCG code operate on
      a pointer to its lower half.
      
      For aarch64-linux-user the only registers we need to share like
      this are the thread-local-storage ones. Widen their fields to
      64 bits and provide the 64 bit reginfo struct to make them
      visible in AArch64 state. Note that minor cleanup of the AArch64
      system register encoding space means We can share the TPIDR_EL1
      reginfo but need split encodings for TPIDR_EL0 and TPIDRRO_EL0.
      
      Since we're touching almost every line in QEMU that uses the
      c13_tls* fields in this patch anyway, we take the opportunity
      to rename them in line with the standard ARM architectural names
      for these registers.
      Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
      Reviewed-by: default avatarRichard Henderson <rth@twiddle.net>
      19917791
  18. 29 Nov, 2013 3 commits
  19. 07 Oct, 2013 2 commits
  20. 24 Sep, 2013 3 commits
  21. 10 Sep, 2013 3 commits
    • Alexander Graf's avatar
      linux-user: Add AArch64 support · 99033cae
      Alexander Graf authored
      This patch adds support for AArch64 in all the small corners of
      linux-user (primarily in image loading and startup code).
      Signed-off-by: default avatarAlexander Graf <agraf@suse.de>
      Signed-off-by: default avatarJohn Rigby <john.rigby@linaro.org>
      Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
      Message-id: 1378235544-22290-22-git-send-email-peter.maydell@linaro.org
      Message-id: 1368505980-17151-11-git-send-email-john.rigby@linaro.org
      [PMM:
       * removed some unnecessary #defines from syscall.h
       * catch attempts to use a 32 bit only cpu with aarch64-linux-user
       * termios stuff moved into its own patch
       * we specify our minimum uname version here now
      ]
      Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
      99033cae
    • Peter Maydell's avatar
      linux-user: Allow targets to specify a minimum uname release · 4a24a758
      Peter Maydell authored
      For newer target architectures, glibc can be picky about the kernel
      version: for example, it will not run on an aarch64 system unless
      the kernel reports itself as at least 3.8.0. Accommodate this by
      enhancing the existing support for faking the kernel version so
      that each target can optionally specify a minimum version: if
      the user doesn't force a specific fake version then we will override
      with the minimum required version only if the real host kernel
      version is insufficient.
      
      Use this facility to let aarch64 report a minimum of 3.8.0.
      Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
      Message-id: 1378235544-22290-21-git-send-email-peter.maydell@linaro.org
      4a24a758
    • Peter Maydell's avatar
      linux-user: Add cpu loop for AArch64 · 1861c454
      Peter Maydell authored
      Add the main linux-user cpu loop for AArch64. Since AArch64
      has a different system call interface, doesn't need to worry
      about FPA emulation and may in the future keep the prefetch/data
      abort information in different system registers, it's simplest
      just to use a completely separate loop from the 32 bit ARM
      target, rather than peppering it with ifdefs.
      Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
      Message-id: 1378235544-22290-14-git-send-email-peter.maydell@linaro.org
      1861c454