1. 28 May, 2014 1 commit
  2. 21 Nov, 2013 2 commits
    • Paolo Bonzini's avatar
      target-i386: yield to another VCPU on PAUSE · b5fc314b
      Paolo Bonzini authored
      After commit b1bbfe72 (aio / timers: On timer modification, qemu_notify
      or aio_notify, 2013-08-21) FreeBSD guests report a huge slowdown.
      
      The problem shows up as soon as FreeBSD turns out its periodic (~1 ms)
      tick, but the timers are only the trigger for a pre-existing problem.
      
      Before the offending patch, setting a timer did a timer_settime system call.
      
      After, setting the timer exits the event loop (which uses poll) and
      reenters it with a new deadline.  This does not cause any slowdown; the
      difference is between one system call (timer_settime and a signal
      delivery (SIGALRM) before the patch, and two system calls afterwards
      (write to a pipe or eventfd + calling poll again when re-entering the
      event loop).
      
      Unfortunately, the exit/enter causes the main loop to grab the iothread
      lock, which in turns kicks the VCPU thread out of execution.  This
      causes TCG to execute the next VCPU in its round-robin scheduling of
      VCPUS.  When the second VCPU is mostly unused, FreeBSD runs a "pause"
      instruction in its idle loop which only burns cycles without any
      progress.  As soon as the timer tick expires, the first VCPU runs
      the interrupt handler but very soon it sets it again---and QEMU
      then goes back doing nothing in the second VCPU.
      
      The fix is to make the pause instruction do "cpu_loop_exit".
      Reported-by: default avatarLuigi Rizzo <rizzo@iet.unipi.it>
      Reviewed-by: default avatarRichard Henderson <rth@twiddle.net>
      Signed-off-by: default avatarPaolo Bonzini <pbonzini@redhat.com>
      b5fc314b
    • Paolo Bonzini's avatar
      target-i386: yield to another VCPU on PAUSE · 81f3053b
      Paolo Bonzini authored
      After commit b1bbfe72 (aio / timers: On timer modification, qemu_notify
      or aio_notify, 2013-08-21) FreeBSD guests report a huge slowdown.
      
      The problem shows up as soon as FreeBSD turns out its periodic (~1 ms)
      tick, but the timers are only the trigger for a pre-existing problem.
      
      Before the offending patch, setting a timer did a timer_settime system call.
      
      After, setting the timer exits the event loop (which uses poll) and
      reenters it with a new deadline.  This does not cause any slowdown; the
      difference is between one system call (timer_settime and a signal
      delivery (SIGALRM) before the patch, and two system calls afterwards
      (write to a pipe or eventfd + calling poll again when re-entering the
      event loop).
      
      Unfortunately, the exit/enter causes the main loop to grab the iothread
      lock, which in turns kicks the VCPU thread out of execution.  This
      causes TCG to execute the next VCPU in its round-robin scheduling of
      VCPUS.  When the second VCPU is mostly unused, FreeBSD runs a "pause"
      instruction in its idle loop which only burns cycles without any
      progress.  As soon as the timer tick expires, the first VCPU runs
      the interrupt handler but very soon it sets it again---and QEMU
      then goes back doing nothing in the second VCPU.
      
      The fix is to make the pause instruction do "cpu_loop_exit".
      
      Cc: Richard Henderson <rth@twiddle.net>
      Reported-by: default avatarLuigi Rizzo <rizzo@iet.unipi.it>
      Signed-off-by: default avatarPaolo Bonzini <pbonzini@redhat.com>
      Reviewed-by: default avatarRichard Henderson <rth@twiddle.net>
      Message-id: 1384948442-24217-1-git-send-email-pbonzini@redhat.com
      Signed-off-by: default avatarAnthony Liguori <aliguori@amazon.com>
      81f3053b
  3. 27 Feb, 2013 1 commit
  4. 20 Feb, 2013 2 commits
  5. 18 Feb, 2013 4 commits
  6. 19 Dec, 2012 1 commit
  7. 28 Oct, 2012 1 commit
  8. 01 Oct, 2012 1 commit
    • H. Peter Anvin's avatar
      x86: Implement SMEP and SMAP · a9321a4d
      H. Peter Anvin authored
      This patch implements Supervisor Mode Execution Prevention (SMEP) and
      Supervisor Mode Access Prevention (SMAP) for x86.  The purpose of the
      patch, obviously, is to help kernel developers debug the support for
      those features.
      
      A fair bit of the code relates to the handling of CPUID features.  The
      CPUID code probably would get greatly simplified if all the feature
      bit words were unified into a single vector object, but in the
      interest of producing a minimal patch for SMEP/SMAP, and because I had
      very limited time for this project, I followed the existing style.
      
      [ v2: don't change the definition of the qemu64 CPU shorthand, since
        that breaks loading old snapshots.  Per Anthony Liguori this can be
        fixed once the CPU feature set is snapshot.
      
        Change the coding style slightly to conform to checkpatch.pl. ]
      Signed-off-by: default avatarH. Peter Anvin <hpa@linux.intel.com>
      Signed-off-by: default avatarAnthony Liguori <aliguori@us.ibm.com>
      a9321a4d
  9. 14 Aug, 2012 8 commits
  10. 28 Jun, 2012 1 commit
    • Blue Swirl's avatar
      x86: avoid AREG0 for exceptions · 77b2bc2c
      Blue Swirl authored
      Add an explicit CPUX86State parameter instead of relying on AREG0.
      
      Merge raise_exception_env() to raise_exception(), likewise with
      raise_exception_err_env() and raise_exception_err().
      
      Introduce cpu_svm_check_intercept_param() and cpu_vmexit()
      as wrappers.
      Signed-off-by: default avatarBlue Swirl <blauwirbel@gmail.com>
      77b2bc2c
  11. 11 Jan, 2012 1 commit
    • Aurelien Jarno's avatar
      target-i386: fix SSE rounding and flush to zero · 2355c16e
      Aurelien Jarno authored
      SSE rounding and flush to zero control has never been implemented. However
      given that softfloat-native was using a single state for FPU and SSE and
      given that glibc is setting both FPU and SSE state in fesetround(), this
      was working correctly up to the switch to softfloat.
      
      Fix that by adding an update_sse_status() function similar to
      update_fpu_status(), and callin git on write to mxcsr.
      Signed-off-by: default avatarAurelien Jarno <aurelien@aurel32.net>
      2355c16e
  12. 23 Oct, 2009 1 commit
  13. 04 Oct, 2009 1 commit
    • Andre Przywara's avatar
      target-i386: add RDTSCP support · 1b050077
      Andre Przywara authored
      RDTSCP reads the time stamp counter and atomically also the content
      of a 32-bit MSR, which can be freely set by the OS. This allows CPU
      local data to be queried by userspace.
      Linux uses this to allow a fast implementation of the getcpu()
      syscall, which uses the vsyscall page to avoid a context switch.
      AMD CPUs since K8RevF and Intel CPUs since Nehalem support this
      instruction.
      RDTSCP is guarded by the RDTSCP CPUID bit (Fn8000_0001:EDX[27]).
      Signed-off-by: default avatarAndre Przywara <andre.przywara@amd.com>
      Signed-off-by: default avatarAurelien Jarno <aurelien@aurel32.net>
      1b050077
  14. 22 May, 2009 1 commit
  15. 17 Nov, 2008 1 commit
  16. 25 Sep, 2008 1 commit
  17. 30 Aug, 2008 1 commit
  18. 18 Jun, 2008 1 commit
  19. 04 Jun, 2008 2 commits
  20. 28 May, 2008 1 commit
  21. 22 May, 2008 2 commits
  22. 21 May, 2008 3 commits
  23. 17 May, 2008 2 commits