1. 30 Oct, 2010 1 commit
  2. 13 Oct, 2010 2 commits
    • Blue Swirl's avatar
      ppc: avoid write only variables · 577f25a5
      Blue Swirl authored
      Compiling with GCC 4.6.0 20100925 produced warnings:
      /src/qemu/target-ppc/op_helper.c: In function 'helper_icbi':
      /src/qemu/target-ppc/op_helper.c:351:14: error: variable 'tmp' set but not used [-Werror=unused-but-set-variable]
      /src/qemu/target-ppc/op_helper.c: In function 'do_6xx_tlb':
      /src/qemu/target-ppc/op_helper.c:3805:28: error: variable 'EPN' set but not used [-Werror=unused-but-set-variable]
      /src/qemu/target-ppc/op_helper.c: In function 'do_74xx_tlb':
      /src/qemu/target-ppc/op_helper.c:3838:28: error: variable 'EPN' set but not used [-Werror=unused-but-set-variable]
      Fix by adding a dummy cast so that the variable is not unused. Delete tmp.
      Signed-off-by: default avatarBlue Swirl <blauwirbel@gmail.com>
    • Blue Swirl's avatar
      ppc: remove video.x · ae0bfb79
      Blue Swirl authored
      Only Mac-on-Linux stuff used video.x, OpenBIOS does not need it.
      Remove video.x MoL hacks.
      Signed-off-by: default avatarAlexander Graf <agraf@suse.de>
      Signed-off-by: default avatarBlue Swirl <blauwirbel@gmail.com>
  3. 05 Oct, 2010 1 commit
  4. 30 Sep, 2010 2 commits
  5. 24 Sep, 2010 1 commit
  6. 17 Sep, 2010 1 commit
  7. 15 Sep, 2010 2 commits
  8. 11 Sep, 2010 1 commit
  9. 05 Sep, 2010 1 commit
    • Alexander Graf's avatar
      KVM: PPC: Add level based interrupt logic · fc87e185
      Alexander Graf authored
      KVM on PowerPC used to have completely broken interrupt logic. Usually,
      interrupts work by having a PIC that pulls a line up/down, so the CPU knows
      that an interrupt is active. This line stays active until some action is
      done to the PIC to release the line.
      On KVM for PPC, we just checked if there was an interrupt pending and pulled
      a line in the kernel module. We never released it though, hoping that kernel
      space would just declare an interrupt as released when injected - which is
      To fix this, we need to completely redesign the interrupt injection logic.
      Whenever an interrupt line gets triggered, we need to notify kernel space
      that the line is up. Whenever it gets released, we do the same. This way
      we can assure that the interrupt state is always known to kernel space.
      This fixes random stalls in KVM guests on PowerPC that were waiting for
      an interrupt while everyone else thought they received it already.
      Signed-off-by: default avatarAlexander Graf <agraf@suse.de>
  10. 26 Aug, 2010 1 commit
    • Alexander Graf's avatar
      PPC: Add PV hypercall transport through fw_cfg · 45024f09
      Alexander Graf authored
      On KVM for PPC we need to tell the guest which instructions to use when
      doing a hypercall. The clean way to do this is to go through an ioctl
      from userspace and passing it on to the guest using the device tree.
      So let's do the qemu part here: read out the hypercall and pass it on
      to the guest's fw_cfg so openBIOS can read it out and expose it again.
      Signed-off-by: default avatarAlexander Graf <agraf@suse.de>
  11. 18 Jul, 2010 1 commit
  12. 13 Jul, 2010 1 commit
  13. 03 Jul, 2010 2 commits
  14. 16 Jun, 2010 1 commit
    • Richard Henderson's avatar
      tcg: Optionally sign-extend 32-bit arguments for 64-bit hosts. · 2bece2c8
      Richard Henderson authored
      Some hosts (amd64, ia64) have an ABI that ignores the high bits
      of the 64-bit register when passing 32-bit arguments.  Others
      require the value to be properly sign-extended for the type.
      I.e. "int32_t" must be sign-extended and "uint32_t" must be
      zero-extended to 64-bits.
      To effect this, extend the "sizemask" parameter to tcg_gen_callN
      to include the signedness of the type of each parameter.  If the
      tcg target requires it, extend each 32-bit argument into a 64-bit
      temp and pass that to the function call.
      This ABI feature is required by sparc64, ppc64 and s390x.
      Signed-off-by: default avatarRichard Henderson <rth@twiddle.net>
      Signed-off-by: default avatarAurelien Jarno <aurelien@aurel32.net>
  15. 31 May, 2010 2 commits
    • Thomas Monjalon's avatar
      target-ppc: remove useless line · 0f89cc7b
      Thomas Monjalon authored
      This line was a bit clear.
      The next lines set or reset this bit (LE) depending of another bit (ILE).
      So the first line is useless.
      Signed-off-by: default avatarThomas Monjalon <thomas@monjalon.net>
      Signed-off-by: default avatarAurelien Jarno <aurelien@aurel32.net>
    • Thomas Monjalon's avatar
      target-ppc: fix RFI by clearing some bits of MSR · c3d420ea
      Thomas Monjalon authored
      Since commit 2ada0ed7, "Return From Interrupt" is broken for PPC processors
      because some interrupt specifics bits of SRR1 are copied to MSR.
      SRR1 is a save of MSR during interrupt.
      During RFI, MSR must be restored from SRR1.
      But some bits of SRR1 are interrupt-specific and are not used for MSR saving.
      This is the specification (ISA 2.06) at chapter 6.4.3 (Interrupt Processing):
      "2. Bits 33:36 and 42:47 of SRR1 or HSRR1 are loaded with information specific
          to the interrupt type.
       3. Bits 0:32, 37:41, and 48:63 of SRR1 or HSRR1 are loaded with a copy of the
          corresponding bits of the MSR."
      Below is a representation of MSR bits which are not saved:
      0:15 16:31 32  33:36    37:41      42:47     48:63
      ——— | ——— | — X X X X — — — — — X X X X X X | ————
      0000 0000 |    7   |   8   |   3   |   F    | 0000
      In the initial Qemu implementation (e1833e1f), the mask 0x783F0000 was used for
      saving MSR in SRR1. But all the bits 32:47 were cleared during RFI restoring.
      This was wrong. The commit 2ada0ed7 explains that this breaks Altivec.
      Indeed, bit 38 (for Altivec support) must be saved and restored.
      The change of 2ada0ed7 was to restore all the bits of SRR1 to MSR.
      But it's also wrong.
      As an example, let's see what's happening after a TLB miss.
      According to the e300 manual (E300CORERM table 5-6), the TLB miss interrupts
      set the bits 44-47 for KEY, I/D, WAY and S/L. These bits are specifics to the
      interrupt and must not be copied into MSR at the end of the interrupt.
      With the current implementation, a TLB miss overwrite bits POW, TGPR and ILE.
      It shouldn't be needed to filter-out bits on MSR saving when interrupt occurs.
      Specific bits overwrite MSR ones in SRR1.
      But at the end of interrupt (RFI), specifics bits must be cleared before
      restoring MSR from SRR1. The mask 0x783F0000 apply here.
      The bits of the mask 0x783F0000 are cleared after an interrupt.
      I cannot find a specification which talks about this
      but I assume it is the truth since Linux can run this way.
      Maybe it's not perfect but it's better (works for e300).
      Signed-off-by: default avatarThomas Monjalon <thomas@monjalon.net>
      Acked-by: default avatarAlexander Graf <agraf@suse.de>
      Signed-off-by: default avatarAurelien Jarno <aurelien@aurel32.net>
  16. 22 May, 2010 1 commit
  17. 18 May, 2010 1 commit
    • Alexander Graf's avatar
      PPC/KVM: make iothread work · c821c2bd
      Alexander Graf authored
      When running with --enable-io-thread the timer we have doesn't help,
      because it doesn't wake up the CPU thread. So instead we need to
      actually kick it.
      While at it I refined the logic a bit to not dumbly trigger a timer
      every 500ms, but rather do it more often after an interrupt got injected.
      If there's no level based interrupt to be expected, we don't need the
      timer anyways.
      This makes qemu-system-ppc with --enable-io-thread work when using KVM.
      Signed-off-by: default avatarAlexander Graf <agraf@suse.de>
      Signed-off-by: default avatarAurelien Jarno <aurelien@aurel32.net>
  18. 11 May, 2010 2 commits
  19. 05 May, 2010 1 commit
  20. 25 Apr, 2010 1 commit
  21. 18 Apr, 2010 1 commit
    • Blue Swirl's avatar
      PPC: avoid function pointer type mismatch, spotted by clang · 7b13448f
      Blue Swirl authored
      Fixes clang errors:
        CC    ppc-softmmu/translate.o
      /src/qemu/target-ppc/translate.c:3748:13: error: comparison of distinct pointer types ('void (*)(void *, int, int)' and 'void *')
              if (likely(read_cb != SPR_NOACCESS)) {
      /src/qemu/target-ppc/translate.c:3748:28: note: instantiated from:
              if (likely(read_cb != SPR_NOACCESS)) {
      /src/qemu/target-ppc/translate.c:3903:13: error: comparison of distinct pointer types ('void (*)(void *, int, int)' and 'void *')
              if (likely(write_cb != SPR_NOACCESS)) {
      /src/qemu/target-ppc/translate.c:3903:29: note: instantiated from:
              if (likely(write_cb != SPR_NOACCESS)) {
      Signed-off-by: default avatarBlue Swirl <blauwirbel@gmail.com>
  22. 26 Mar, 2010 1 commit
  23. 16 Mar, 2010 1 commit
    • Paul Brook's avatar
      Large page TLB flush · d4c430a8
      Paul Brook authored
      QEMU uses a fixed page size for the CPU TLB.  If the guest uses large
      pages then we effectively split these into multiple smaller pages, and
      populate the corresponding TLB entries on demand.
      When the guest invalidates the TLB by virtual address we must invalidate
      all entries covered by the large page.  However the address used to
      invalidate the entry may not be present in the QEMU TLB, so we do not
      know which regions to clear.
      Implementing a full vaiable size TLB is hard and slow, so just keep a
      simple address/mask pair to record which addresses may have been mapped by
      large pages.  If the guest invalidates this region then flush the
      whole TLB.
      Signed-off-by: default avatarPaul Brook <paul@codesourcery.com>
  24. 12 Mar, 2010 3 commits
  25. 11 Mar, 2010 3 commits
  26. 03 Mar, 2010 1 commit
    • Jan Kiszka's avatar
      KVM: Rework VCPU state writeback API · ea375f9a
      Jan Kiszka authored
      This grand cleanup drops all reset and vmsave/load related
      synchronization points in favor of four(!) generic hooks:
      - cpu_synchronize_all_states in qemu_savevm_state_complete
        (initial sync from kernel before vmsave)
      - cpu_synchronize_all_post_init in qemu_loadvm_state
        (writeback after vmload)
      - cpu_synchronize_all_post_init in main after machine init
      - cpu_synchronize_all_post_reset in qemu_system_reset
        (writeback after system reset)
      These writeback points + the existing one of VCPU exec after
      cpu_synchronize_state map on three levels of writeback:
      - KVM_PUT_RUNTIME_STATE (during runtime, other VCPUs continue to run)
      - KVM_PUT_RESET_STATE   (on synchronous system reset, all VCPUs stopped)
      - KVM_PUT_FULL_STATE    (on init or vmload, all VCPUs stopped as well)
      This level is passed to the arch-specific VCPU state writing function
      that will decide which concrete substates need to be written. That way,
      no writer of load, save or reset functions that interact with in-kernel
      KVM states will ever have to worry about synchronization again. That
      also means that a lot of reasons for races, segfaults and deadlocks are
      cpu_synchronize_state remains untouched, just as Anthony suggested. We
      continue to need it before reading or writing of VCPU states that are
      also tracked by in-kernel KVM subsystems.
      Consequently, this patch removes many cpu_synchronize_state calls that
      are now redundant, just like remaining explicit register syncs.
      Signed-off-by: default avatarJan Kiszka <jan.kiszka@siemens.com>
      Signed-off-by: default avatarMarcelo Tosatti <mtosatti@redhat.com>
  27. 28 Feb, 2010 3 commits
  28. 27 Feb, 2010 1 commit