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/*
 *  i386 CPUID helper functions
 *
 *  Copyright (c) 2003 Fabrice Bellard
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
 */
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <inttypes.h>

#include "cpu.h"
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#include "sysemu/kvm.h"
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#include "sysemu/cpus.h"
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#include "kvm_i386.h"
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#include "topology.h"
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#include "qemu/option.h"
#include "qemu/config-file.h"
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#include "qapi/qmp/qerror.h"
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#include "qapi-types.h"
#include "qapi-visit.h"
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#include "qapi/visitor.h"
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#include "sysemu/arch_init.h"
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#include "hw/hw.h"
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#if defined(CONFIG_KVM)
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#include <linux/kvm_para.h>
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#endif
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#include "sysemu/sysemu.h"
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#include "hw/qdev-properties.h"
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#include "hw/cpu/icc_bus.h"
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#ifndef CONFIG_USER_ONLY
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#include "hw/xen/xen.h"
#include "hw/i386/apic_internal.h"
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#endif

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/* Cache topology CPUID constants: */

/* CPUID Leaf 2 Descriptors */

#define CPUID_2_L1D_32KB_8WAY_64B 0x2c
#define CPUID_2_L1I_32KB_8WAY_64B 0x30
#define CPUID_2_L2_2MB_8WAY_64B   0x7d


/* CPUID Leaf 4 constants: */

/* EAX: */
#define CPUID_4_TYPE_DCACHE  1
#define CPUID_4_TYPE_ICACHE  2
#define CPUID_4_TYPE_UNIFIED 3

#define CPUID_4_LEVEL(l)          ((l) << 5)

#define CPUID_4_SELF_INIT_LEVEL (1 << 8)
#define CPUID_4_FULLY_ASSOC     (1 << 9)

/* EDX: */
#define CPUID_4_NO_INVD_SHARING (1 << 0)
#define CPUID_4_INCLUSIVE       (1 << 1)
#define CPUID_4_COMPLEX_IDX     (1 << 2)

#define ASSOC_FULL 0xFF

/* AMD associativity encoding used on CPUID Leaf 0x80000006: */
#define AMD_ENC_ASSOC(a) (a <=   1 ? a   : \
                          a ==   2 ? 0x2 : \
                          a ==   4 ? 0x4 : \
                          a ==   8 ? 0x6 : \
                          a ==  16 ? 0x8 : \
                          a ==  32 ? 0xA : \
                          a ==  48 ? 0xB : \
                          a ==  64 ? 0xC : \
                          a ==  96 ? 0xD : \
                          a == 128 ? 0xE : \
                          a == ASSOC_FULL ? 0xF : \
                          0 /* invalid value */)


/* Definitions of the hardcoded cache entries we expose: */

/* L1 data cache: */
#define L1D_LINE_SIZE         64
#define L1D_ASSOCIATIVITY      8
#define L1D_SETS              64
#define L1D_PARTITIONS         1
/* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 32KiB */
#define L1D_DESCRIPTOR CPUID_2_L1D_32KB_8WAY_64B
/*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
#define L1D_LINES_PER_TAG      1
#define L1D_SIZE_KB_AMD       64
#define L1D_ASSOCIATIVITY_AMD  2

/* L1 instruction cache: */
#define L1I_LINE_SIZE         64
#define L1I_ASSOCIATIVITY      8
#define L1I_SETS              64
#define L1I_PARTITIONS         1
/* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 32KiB */
#define L1I_DESCRIPTOR CPUID_2_L1I_32KB_8WAY_64B
/*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
#define L1I_LINES_PER_TAG      1
#define L1I_SIZE_KB_AMD       64
#define L1I_ASSOCIATIVITY_AMD  2

/* Level 2 unified cache: */
#define L2_LINE_SIZE          64
#define L2_ASSOCIATIVITY      16
#define L2_SETS             4096
#define L2_PARTITIONS          1
/* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 4MiB */
/*FIXME: CPUID leaf 2 descriptor is inconsistent with CPUID leaf 4 */
#define L2_DESCRIPTOR CPUID_2_L2_2MB_8WAY_64B
/*FIXME: CPUID leaf 0x80000006 is inconsistent with leaves 2 & 4 */
#define L2_LINES_PER_TAG       1
#define L2_SIZE_KB_AMD       512

/* No L3 cache: */
#define L3_SIZE_KB             0 /* disabled */
#define L3_ASSOCIATIVITY       0 /* disabled */
#define L3_LINES_PER_TAG       0 /* disabled */
#define L3_LINE_SIZE           0 /* disabled */

/* TLB definitions: */

#define L1_DTLB_2M_ASSOC       1
#define L1_DTLB_2M_ENTRIES   255
#define L1_DTLB_4K_ASSOC       1
#define L1_DTLB_4K_ENTRIES   255

#define L1_ITLB_2M_ASSOC       1
#define L1_ITLB_2M_ENTRIES   255
#define L1_ITLB_4K_ASSOC       1
#define L1_ITLB_4K_ENTRIES   255

#define L2_DTLB_2M_ASSOC       0 /* disabled */
#define L2_DTLB_2M_ENTRIES     0 /* disabled */
#define L2_DTLB_4K_ASSOC       4
#define L2_DTLB_4K_ENTRIES   512

#define L2_ITLB_2M_ASSOC       0 /* disabled */
#define L2_ITLB_2M_ENTRIES     0 /* disabled */
#define L2_ITLB_4K_ASSOC       4
#define L2_ITLB_4K_ENTRIES   512



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static void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,
                                     uint32_t vendor2, uint32_t vendor3)
{
    int i;
    for (i = 0; i < 4; i++) {
        dst[i] = vendor1 >> (8 * i);
        dst[i + 4] = vendor2 >> (8 * i);
        dst[i + 8] = vendor3 >> (8 * i);
    }
    dst[CPUID_VENDOR_SZ] = '\0';
}

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/* feature flags taken from "Intel Processor Identification and the CPUID
 * Instruction" and AMD's "CPUID Specification".  In cases of disagreement
 * between feature naming conventions, aliases may be added.
 */
static const char *feature_name[] = {
    "fpu", "vme", "de", "pse",
    "tsc", "msr", "pae", "mce",
    "cx8", "apic", NULL, "sep",
    "mtrr", "pge", "mca", "cmov",
    "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */,
    NULL, "ds" /* Intel dts */, "acpi", "mmx",
    "fxsr", "sse", "sse2", "ss",
    "ht" /* Intel htt */, "tm", "ia64", "pbe",
};
static const char *ext_feature_name[] = {
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    "pni|sse3" /* Intel,AMD sse3 */, "pclmulqdq|pclmuldq", "dtes64", "monitor",
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    "ds_cpl", "vmx", "smx", "est",
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    "tm2", "ssse3", "cid", NULL,
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    "fma", "cx16", "xtpr", "pdcm",
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    NULL, "pcid", "dca", "sse4.1|sse4_1",
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    "sse4.2|sse4_2", "x2apic", "movbe", "popcnt",
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    "tsc-deadline", "aes", "xsave", "osxsave",
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    "avx", "f16c", "rdrand", "hypervisor",
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};
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/* Feature names that are already defined on feature_name[] but are set on
 * CPUID[8000_0001].EDX on AMD CPUs don't have their names on
 * ext2_feature_name[]. They are copied automatically to cpuid_ext2_features
 * if and only if CPU vendor is AMD.
 */
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static const char *ext2_feature_name[] = {
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    NULL /* fpu */, NULL /* vme */, NULL /* de */, NULL /* pse */,
    NULL /* tsc */, NULL /* msr */, NULL /* pae */, NULL /* mce */,
    NULL /* cx8 */ /* AMD CMPXCHG8B */, NULL /* apic */, NULL, "syscall",
    NULL /* mtrr */, NULL /* pge */, NULL /* mca */, NULL /* cmov */,
    NULL /* pat */, NULL /* pse36 */, NULL, NULL /* Linux mp */,
    "nx|xd", NULL, "mmxext", NULL /* mmx */,
    NULL /* fxsr */, "fxsr_opt|ffxsr", "pdpe1gb" /* AMD Page1GB */, "rdtscp",
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    NULL, "lm|i64", "3dnowext", "3dnow",
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};
static const char *ext3_feature_name[] = {
    "lahf_lm" /* AMD LahfSahf */, "cmp_legacy", "svm", "extapic" /* AMD ExtApicSpace */,
    "cr8legacy" /* AMD AltMovCr8 */, "abm", "sse4a", "misalignsse",
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    "3dnowprefetch", "osvw", "ibs", "xop",
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    "skinit", "wdt", NULL, "lwp",
    "fma4", "tce", NULL, "nodeid_msr",
    NULL, "tbm", "topoext", "perfctr_core",
    "perfctr_nb", NULL, NULL, NULL,
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    NULL, NULL, NULL, NULL,
};

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static const char *ext4_feature_name[] = {
    NULL, NULL, "xstore", "xstore-en",
    NULL, NULL, "xcrypt", "xcrypt-en",
    "ace2", "ace2-en", "phe", "phe-en",
    "pmm", "pmm-en", NULL, NULL,
    NULL, NULL, NULL, NULL,
    NULL, NULL, NULL, NULL,
    NULL, NULL, NULL, NULL,
    NULL, NULL, NULL, NULL,
};

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static const char *kvm_feature_name[] = {
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    "kvmclock", "kvm_nopiodelay", "kvm_mmu", "kvmclock",
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    "kvm_asyncpf", "kvm_steal_time", "kvm_pv_eoi", "kvm_pv_unhalt",
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    NULL, NULL, NULL, NULL,
    NULL, NULL, NULL, NULL,
    NULL, NULL, NULL, NULL,
    NULL, NULL, NULL, NULL,
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    "kvmclock-stable-bit", NULL, NULL, NULL,
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    NULL, NULL, NULL, NULL,
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};

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static const char *svm_feature_name[] = {
    "npt", "lbrv", "svm_lock", "nrip_save",
    "tsc_scale", "vmcb_clean",  "flushbyasid", "decodeassists",
    NULL, NULL, "pause_filter", NULL,
    "pfthreshold", NULL, NULL, NULL,
    NULL, NULL, NULL, NULL,
    NULL, NULL, NULL, NULL,
    NULL, NULL, NULL, NULL,
    NULL, NULL, NULL, NULL,
};

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static const char *cpuid_7_0_ebx_feature_name[] = {
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    "fsgsbase", "tsc_adjust", NULL, "bmi1", "hle", "avx2", NULL, "smep",
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    "bmi2", "erms", "invpcid", "rtm", NULL, NULL, "mpx", NULL,
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    "avx512f", NULL, "rdseed", "adx", "smap", NULL, NULL, NULL,
    NULL, NULL, "avx512pf", "avx512er", "avx512cd", NULL, NULL, NULL,
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};

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static const char *cpuid_apm_edx_feature_name[] = {
    NULL, NULL, NULL, NULL,
    NULL, NULL, NULL, NULL,
    "invtsc", NULL, NULL, NULL,
    NULL, NULL, NULL, NULL,
    NULL, NULL, NULL, NULL,
    NULL, NULL, NULL, NULL,
    NULL, NULL, NULL, NULL,
    NULL, NULL, NULL, NULL,
};

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#define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE)
#define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \
          CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC)
#define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \
          CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
          CPUID_PSE36 | CPUID_FXSR)
#define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE)
#define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \
          CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \
          CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \
          CPUID_PAE | CPUID_SEP | CPUID_APIC)

#define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \
          CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \
          CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
          CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \
          CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS)
          /* partly implemented:
          CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64) */
          /* missing:
          CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */
#define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | \
          CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | \
          CPUID_EXT_SSE41 | CPUID_EXT_SSE42 | CPUID_EXT_POPCNT | \
          CPUID_EXT_MOVBE | CPUID_EXT_AES | CPUID_EXT_HYPERVISOR)
          /* missing:
          CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_SMX,
          CPUID_EXT_EST, CPUID_EXT_TM2, CPUID_EXT_CID, CPUID_EXT_FMA,
          CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_PCID, CPUID_EXT_DCA,
          CPUID_EXT_X2APIC, CPUID_EXT_TSC_DEADLINE_TIMER, CPUID_EXT_XSAVE,
          CPUID_EXT_OSXSAVE, CPUID_EXT_AVX, CPUID_EXT_F16C,
          CPUID_EXT_RDRAND */

#ifdef TARGET_X86_64
#define TCG_EXT2_X86_64_FEATURES (CPUID_EXT2_SYSCALL | CPUID_EXT2_LM)
#else
#define TCG_EXT2_X86_64_FEATURES 0
#endif

#define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \
          CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \
          CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_PDPE1GB | \
          TCG_EXT2_X86_64_FEATURES)
#define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \
          CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A)
#define TCG_EXT4_FEATURES 0
#define TCG_SVM_FEATURES 0
#define TCG_KVM_FEATURES 0
#define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP | \
          CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ADX)
          /* missing:
          CPUID_7_0_EBX_FSGSBASE, CPUID_7_0_EBX_HLE, CPUID_7_0_EBX_AVX2,
          CPUID_7_0_EBX_ERMS, CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM,
          CPUID_7_0_EBX_RDSEED */
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#define TCG_APM_FEATURES 0
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typedef struct FeatureWordInfo {
    const char **feat_names;
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    uint32_t cpuid_eax;   /* Input EAX for CPUID */
    bool cpuid_needs_ecx; /* CPUID instruction uses ECX as input */
    uint32_t cpuid_ecx;   /* Input ECX value for CPUID */
    int cpuid_reg;        /* output register (R_* constant) */
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    uint32_t tcg_features; /* Feature flags supported by TCG */
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    uint32_t unmigratable_flags; /* Feature flags known to be unmigratable */
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} FeatureWordInfo;

static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
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    [FEAT_1_EDX] = {
        .feat_names = feature_name,
        .cpuid_eax = 1, .cpuid_reg = R_EDX,
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        .tcg_features = TCG_FEATURES,
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    },
    [FEAT_1_ECX] = {
        .feat_names = ext_feature_name,
        .cpuid_eax = 1, .cpuid_reg = R_ECX,
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        .tcg_features = TCG_EXT_FEATURES,
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    },
    [FEAT_8000_0001_EDX] = {
        .feat_names = ext2_feature_name,
        .cpuid_eax = 0x80000001, .cpuid_reg = R_EDX,
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        .tcg_features = TCG_EXT2_FEATURES,
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    },
    [FEAT_8000_0001_ECX] = {
        .feat_names = ext3_feature_name,
        .cpuid_eax = 0x80000001, .cpuid_reg = R_ECX,
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        .tcg_features = TCG_EXT3_FEATURES,
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    },
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    [FEAT_C000_0001_EDX] = {
        .feat_names = ext4_feature_name,
        .cpuid_eax = 0xC0000001, .cpuid_reg = R_EDX,
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        .tcg_features = TCG_EXT4_FEATURES,
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    },
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    [FEAT_KVM] = {
        .feat_names = kvm_feature_name,
        .cpuid_eax = KVM_CPUID_FEATURES, .cpuid_reg = R_EAX,
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        .tcg_features = TCG_KVM_FEATURES,
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    },
    [FEAT_SVM] = {
        .feat_names = svm_feature_name,
        .cpuid_eax = 0x8000000A, .cpuid_reg = R_EDX,
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        .tcg_features = TCG_SVM_FEATURES,
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    },
    [FEAT_7_0_EBX] = {
        .feat_names = cpuid_7_0_ebx_feature_name,
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        .cpuid_eax = 7,
        .cpuid_needs_ecx = true, .cpuid_ecx = 0,
        .cpuid_reg = R_EBX,
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        .tcg_features = TCG_7_0_EBX_FEATURES,
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    },
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    [FEAT_8000_0007_EDX] = {
        .feat_names = cpuid_apm_edx_feature_name,
        .cpuid_eax = 0x80000007,
        .cpuid_reg = R_EDX,
        .tcg_features = TCG_APM_FEATURES,
        .unmigratable_flags = CPUID_APM_INVTSC,
    },
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};

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typedef struct X86RegisterInfo32 {
    /* Name of register */
    const char *name;
    /* QAPI enum value register */
    X86CPURegister32 qapi_enum;
} X86RegisterInfo32;

#define REGISTER(reg) \
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    [R_##reg] = { .name = #reg, .qapi_enum = X86_CPU_REGISTER32_##reg }
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static const X86RegisterInfo32 x86_reg_info_32[CPU_NB_REGS32] = {
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    REGISTER(EAX),
    REGISTER(ECX),
    REGISTER(EDX),
    REGISTER(EBX),
    REGISTER(ESP),
    REGISTER(EBP),
    REGISTER(ESI),
    REGISTER(EDI),
};
#undef REGISTER

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typedef struct ExtSaveArea {
    uint32_t feature, bits;
    uint32_t offset, size;
} ExtSaveArea;

static const ExtSaveArea ext_save_areas[] = {
    [2] = { .feature = FEAT_1_ECX, .bits = CPUID_EXT_AVX,
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            .offset = 0x240, .size = 0x100 },
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    [3] = { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
            .offset = 0x3c0, .size = 0x40  },
    [4] = { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
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            .offset = 0x400, .size = 0x40  },
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    [5] = { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
            .offset = 0x440, .size = 0x40 },
    [6] = { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
            .offset = 0x480, .size = 0x200 },
    [7] = { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
            .offset = 0x680, .size = 0x400 },
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};
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const char *get_register_name_32(unsigned int reg)
{
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    if (reg >= CPU_NB_REGS32) {
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        return NULL;
    }
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    return x86_reg_info_32[reg].name;
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}

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/* KVM-specific features that are automatically added to all CPU models
 * when KVM is enabled.
 */
static uint32_t kvm_default_features[FEATURE_WORDS] = {
    [FEAT_KVM] = (1 << KVM_FEATURE_CLOCKSOURCE) |
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        (1 << KVM_FEATURE_NOP_IO_DELAY) |
        (1 << KVM_FEATURE_CLOCKSOURCE2) |
        (1 << KVM_FEATURE_ASYNC_PF) |
        (1 << KVM_FEATURE_STEAL_TIME) |
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        (1 << KVM_FEATURE_PV_EOI) |
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        (1 << KVM_FEATURE_CLOCKSOURCE_STABLE_BIT),
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    [FEAT_1_ECX] = CPUID_EXT_X2APIC,
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};
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/* Features that are not added by default to any CPU model when KVM is enabled.
 */
static uint32_t kvm_default_unset_features[FEATURE_WORDS] = {
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    [FEAT_1_EDX] = CPUID_ACPI,
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    [FEAT_1_ECX] = CPUID_EXT_MONITOR,
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    [FEAT_8000_0001_ECX] = CPUID_EXT3_SVM,
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};

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void x86_cpu_compat_kvm_no_autoenable(FeatureWord w, uint32_t features)
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{
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    kvm_default_features[w] &= ~features;
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}

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void x86_cpu_compat_kvm_no_autodisable(FeatureWord w, uint32_t features)
{
    kvm_default_unset_features[w] &= ~features;
}

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/*
 * Returns the set of feature flags that are supported and migratable by
 * QEMU, for a given FeatureWord.
 */
static uint32_t x86_cpu_get_migratable_flags(FeatureWord w)
{
    FeatureWordInfo *wi = &feature_word_info[w];
    uint32_t r = 0;
    int i;

    for (i = 0; i < 32; i++) {
        uint32_t f = 1U << i;
        /* If the feature name is unknown, it is not supported by QEMU yet */
        if (!wi->feat_names[i]) {
            continue;
        }
        /* Skip features known to QEMU, but explicitly marked as unmigratable */
        if (wi->unmigratable_flags & f) {
            continue;
        }
        r |= f;
    }
    return r;
}

502 503
void host_cpuid(uint32_t function, uint32_t count,
                uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx)
504
{
505 506 507 508 509 510 511
    uint32_t vec[4];

#ifdef __x86_64__
    asm volatile("cpuid"
                 : "=a"(vec[0]), "=b"(vec[1]),
                   "=c"(vec[2]), "=d"(vec[3])
                 : "0"(function), "c"(count) : "cc");
512
#elif defined(__i386__)
513 514 515 516 517 518 519 520 521
    asm volatile("pusha \n\t"
                 "cpuid \n\t"
                 "mov %%eax, 0(%2) \n\t"
                 "mov %%ebx, 4(%2) \n\t"
                 "mov %%ecx, 8(%2) \n\t"
                 "mov %%edx, 12(%2) \n\t"
                 "popa"
                 : : "a"(function), "c"(count), "S"(vec)
                 : "memory", "cc");
522 523
#else
    abort();
524 525
#endif

526
    if (eax)
527
        *eax = vec[0];
528
    if (ebx)
529
        *ebx = vec[1];
530
    if (ecx)
531
        *ecx = vec[2];
532
    if (edx)
533
        *edx = vec[3];
534
}
535 536 537 538 539 540 541 542

#define iswhite(c) ((c) && ((c) <= ' ' || '~' < (c)))

/* general substring compare of *[s1..e1) and *[s2..e2).  sx is start of
 * a substring.  ex if !NULL points to the first char after a substring,
 * otherwise the string is assumed to sized by a terminating nul.
 * Return lexical ordering of *s1:*s2.
 */
543 544
static int sstrcmp(const char *s1, const char *e1,
                   const char *s2, const char *e2)
545 546 547 548 549 550 551 552 553 554 555 556 557 558 559 560 561 562 563 564 565 566 567 568 569 570 571 572 573 574 575 576 577 578 579 580
{
    for (;;) {
        if (!*s1 || !*s2 || *s1 != *s2)
            return (*s1 - *s2);
        ++s1, ++s2;
        if (s1 == e1 && s2 == e2)
            return (0);
        else if (s1 == e1)
            return (*s2);
        else if (s2 == e2)
            return (*s1);
    }
}

/* compare *[s..e) to *altstr.  *altstr may be a simple string or multiple
 * '|' delimited (possibly empty) strings in which case search for a match
 * within the alternatives proceeds left to right.  Return 0 for success,
 * non-zero otherwise.
 */
static int altcmp(const char *s, const char *e, const char *altstr)
{
    const char *p, *q;

    for (q = p = altstr; ; ) {
        while (*p && *p != '|')
            ++p;
        if ((q == p && !*s) || (q != p && !sstrcmp(s, e, q, p)))
            return (0);
        if (!*p)
            return (1);
        else
            q = ++p;
    }
}

/* search featureset for flag *[s..e), if found set corresponding bit in
581
 * *pval and return true, otherwise return false
582
 */
583 584
static bool lookup_feature(uint32_t *pval, const char *s, const char *e,
                           const char **featureset)
585 586 587
{
    uint32_t mask;
    const char **ppc;
588
    bool found = false;
589

590
    for (mask = 1, ppc = featureset; mask; mask <<= 1, ++ppc) {
591 592
        if (*ppc && !altcmp(s, e, *ppc)) {
            *pval |= mask;
593
            found = true;
594
        }
595 596
    }
    return found;
597 598
}

599
static void add_flagname_to_bitmaps(const char *flagname,
600 601
                                    FeatureWordArray words,
                                    Error **errp)
602
{
603 604 605 606 607 608 609 610 611
    FeatureWord w;
    for (w = 0; w < FEATURE_WORDS; w++) {
        FeatureWordInfo *wi = &feature_word_info[w];
        if (wi->feat_names &&
            lookup_feature(&words[w], flagname, NULL, wi->feat_names)) {
            break;
        }
    }
    if (w == FEATURE_WORDS) {
612
        error_setg(errp, "CPU feature %s not found", flagname);
613
    }
614 615
}

616 617 618 619 620 621 622 623 624 625 626 627 628
/* CPU class name definitions: */

#define X86_CPU_TYPE_SUFFIX "-" TYPE_X86_CPU
#define X86_CPU_TYPE_NAME(name) (name X86_CPU_TYPE_SUFFIX)

/* Return type name for a given CPU model name
 * Caller is responsible for freeing the returned string.
 */
static char *x86_cpu_type_name(const char *model_name)
{
    return g_strdup_printf(X86_CPU_TYPE_NAME("%s"), model_name);
}

629 630
static ObjectClass *x86_cpu_class_by_name(const char *cpu_model)
{
631 632 633
    ObjectClass *oc;
    char *typename;

634 635 636 637
    if (cpu_model == NULL) {
        return NULL;
    }

638 639 640 641
    typename = x86_cpu_type_name(cpu_model);
    oc = object_class_by_name(typename);
    g_free(typename);
    return oc;
642 643
}

644
struct X86CPUDefinition {
645 646
    const char *name;
    uint32_t level;
647 648
    uint32_t xlevel;
    uint32_t xlevel2;
649 650
    /* vendor is zero-terminated, 12 character ASCII string */
    char vendor[CPUID_VENDOR_SZ + 1];
651 652 653
    int family;
    int model;
    int stepping;
654
    FeatureWordArray features;
655
    char model_id[48];
656
    bool cache_info_passthrough;
657
};
658

659
static X86CPUDefinition builtin_x86_defs[] = {
660 661 662
    {
        .name = "qemu64",
        .level = 4,
663
        .vendor = CPUID_VENDOR_AMD,
664
        .family = 6,
665
        .model = 6,
666
        .stepping = 3,
667
        .features[FEAT_1_EDX] =
668
            PPRO_FEATURES |
669 670
            CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
            CPUID_PSE36,
671
        .features[FEAT_1_ECX] =
672
            CPUID_EXT_SSE3 | CPUID_EXT_CX16 | CPUID_EXT_POPCNT,
673
        .features[FEAT_8000_0001_EDX] =
674
            (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
675
            CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
676
        .features[FEAT_8000_0001_ECX] =
677
            CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
678 679 680 681 682 683
            CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
        .xlevel = 0x8000000A,
    },
    {
        .name = "phenom",
        .level = 5,
684
        .vendor = CPUID_VENDOR_AMD,
685 686 687
        .family = 16,
        .model = 2,
        .stepping = 3,
688
        /* Missing: CPUID_HT */
689
        .features[FEAT_1_EDX] =
690
            PPRO_FEATURES |
691
            CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
692
            CPUID_PSE36 | CPUID_VME,
693
        .features[FEAT_1_ECX] =
694
            CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 |
695
            CPUID_EXT_POPCNT,
696
        .features[FEAT_8000_0001_EDX] =
697
            (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
698 699
            CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX |
            CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT |
700
            CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP,
701 702 703 704
        /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
                    CPUID_EXT3_CR8LEG,
                    CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
                    CPUID_EXT3_OSVW, CPUID_EXT3_IBS */
705
        .features[FEAT_8000_0001_ECX] =
706
            CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
707
            CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
708
        /* Missing: CPUID_SVM_LBRV */
709
        .features[FEAT_SVM] =
710
            CPUID_SVM_NPT,
711 712 713 714 715 716
        .xlevel = 0x8000001A,
        .model_id = "AMD Phenom(tm) 9550 Quad-Core Processor"
    },
    {
        .name = "core2duo",
        .level = 10,
717
        .vendor = CPUID_VENDOR_INTEL,
718 719 720
        .family = 6,
        .model = 15,
        .stepping = 11,
721
        /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
722
        .features[FEAT_1_EDX] =
723
            PPRO_FEATURES |
724
            CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
725 726
            CPUID_PSE36 | CPUID_VME | CPUID_ACPI | CPUID_SS,
        /* Missing: CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_EST,
727
         * CPUID_EXT_TM2, CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_VMX */
728
        .features[FEAT_1_ECX] =
729
            CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
730
            CPUID_EXT_CX16,
731
        .features[FEAT_8000_0001_EDX] =
732
            CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
733
        .features[FEAT_8000_0001_ECX] =
734
            CPUID_EXT3_LAHF_LM,
735 736 737 738 739 740
        .xlevel = 0x80000008,
        .model_id = "Intel(R) Core(TM)2 Duo CPU     T7700  @ 2.40GHz",
    },
    {
        .name = "kvm64",
        .level = 5,
741
        .vendor = CPUID_VENDOR_INTEL,
742 743 744 745
        .family = 15,
        .model = 6,
        .stepping = 1,
        /* Missing: CPUID_VME, CPUID_HT */
746
        .features[FEAT_1_EDX] =
747
            PPRO_FEATURES |
748 749 750
            CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
            CPUID_PSE36,
        /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */
751
        .features[FEAT_1_ECX] =
752
            CPUID_EXT_SSE3 | CPUID_EXT_CX16,
753
        /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */
754
        .features[FEAT_8000_0001_EDX] =
755
            (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
756 757 758 759 760
            CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
        /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
                    CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A,
                    CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
                    CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */
761
        .features[FEAT_8000_0001_ECX] =
762
            0,
763 764 765 766 767 768
        .xlevel = 0x80000008,
        .model_id = "Common KVM processor"
    },
    {
        .name = "qemu32",
        .level = 4,
769
        .vendor = CPUID_VENDOR_INTEL,
770
        .family = 6,
771
        .model = 6,
772
        .stepping = 3,
773
        .features[FEAT_1_EDX] =
774
            PPRO_FEATURES,
775
        .features[FEAT_1_ECX] =
776
            CPUID_EXT_SSE3 | CPUID_EXT_POPCNT,
777
        .xlevel = 0x80000004,
778
    },
779 780 781
    {
        .name = "kvm32",
        .level = 5,
782
        .vendor = CPUID_VENDOR_INTEL,
783 784 785
        .family = 15,
        .model = 6,
        .stepping = 1,
786
        .features[FEAT_1_EDX] =
787
            PPRO_FEATURES |
788
            CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36,
789
        .features[FEAT_1_ECX] =
790
            CPUID_EXT_SSE3,
791
        .features[FEAT_8000_0001_EDX] =
792
            PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES,
793
        .features[FEAT_8000_0001_ECX] =
794
            0,
795 796 797
        .xlevel = 0x80000008,
        .model_id = "Common 32-bit KVM processor"
    },
798 799 800
    {
        .name = "coreduo",
        .level = 10,
801
        .vendor = CPUID_VENDOR_INTEL,
802 803 804
        .family = 6,
        .model = 14,
        .stepping = 8,
805
        /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
806
        .features[FEAT_1_EDX] =
807
            PPRO_FEATURES | CPUID_VME |
808 809 810
            CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_ACPI |
            CPUID_SS,
        /* Missing: CPUID_EXT_EST, CPUID_EXT_TM2 , CPUID_EXT_XTPR,
811
         * CPUID_EXT_PDCM, CPUID_EXT_VMX */
812
        .features[FEAT_1_ECX] =
813
            CPUID_EXT_SSE3 | CPUID_EXT_MONITOR,
814
        .features[FEAT_8000_0001_EDX] =
815
            CPUID_EXT2_NX,
816 817 818 819 820
        .xlevel = 0x80000008,
        .model_id = "Genuine Intel(R) CPU           T2600  @ 2.16GHz",
    },
    {
        .name = "486",
821
        .level = 1,
822
        .vendor = CPUID_VENDOR_INTEL,
823
        .family = 4,
824
        .model = 8,
825
        .stepping = 0,
826
        .features[FEAT_1_EDX] =
827
            I486_FEATURES,
828 829 830 831 832
        .xlevel = 0,
    },
    {
        .name = "pentium",
        .level = 1,
833
        .vendor = CPUID_VENDOR_INTEL,
834 835 836
        .family = 5,
        .model = 4,
        .stepping = 3,
837
        .features[FEAT_1_EDX] =
838
            PENTIUM_FEATURES,
839 840 841 842 843
        .xlevel = 0,
    },
    {
        .name = "pentium2",
        .level = 2,
844
        .vendor = CPUID_VENDOR_INTEL,
845 846 847
        .family = 6,
        .model = 5,
        .stepping = 2,
848
        .features[FEAT_1_EDX] =
849
            PENTIUM2_FEATURES,
850 851 852 853 854
        .xlevel = 0,
    },
    {
        .name = "pentium3",
        .level = 2,
855
        .vendor = CPUID_VENDOR_INTEL,
856 857 858
        .family = 6,
        .model = 7,
        .stepping = 3,
859
        .features[FEAT_1_EDX] =
860
            PENTIUM3_FEATURES,
861 862 863 864 865
        .xlevel = 0,
    },
    {
        .name = "athlon",
        .level = 2,
866
        .vendor = CPUID_VENDOR_AMD,
867 868 869
        .family = 6,
        .model = 2,
        .stepping = 3,
870
        .features[FEAT_1_EDX] =
871
            PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR |
872
            CPUID_MCA,
873
        .features[FEAT_8000_0001_EDX] =
874
            (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
875
            CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT,
876 877 878 879 880 881
        .xlevel = 0x80000008,
    },
    {
        .name = "n270",
        /* original is on level 10 */
        .level = 5,
882
        .vendor = CPUID_VENDOR_INTEL,
883 884 885
        .family = 6,
        .model = 28,
        .stepping = 2,
886
        /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
887
        .features[FEAT_1_EDX] =
888
            PPRO_FEATURES |
889 890
            CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME |
            CPUID_ACPI | CPUID_SS,
891
            /* Some CPUs got no CPUID_SEP */
892 893
        /* Missing: CPUID_EXT_DSCPL, CPUID_EXT_EST, CPUID_EXT_TM2,
         * CPUID_EXT_XTPR */
894
        .features[FEAT_1_ECX] =
895
            CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
896
            CPUID_EXT_MOVBE,
897
        .features[FEAT_8000_0001_EDX] =
898
            (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
899
            CPUID_EXT2_NX,
900
        .features[FEAT_8000_0001_ECX] =
901
            CPUID_EXT3_LAHF_LM,
902 903 904
        .xlevel = 0x8000000A,
        .model_id = "Intel(R) Atom(TM) CPU N270   @ 1.60GHz",
    },
905 906
    {
        .name = "Conroe",
907
        .level = 4,
908
        .vendor = CPUID_VENDOR_INTEL,
909
        .family = 6,
910
        .model = 15,
911
        .stepping = 3,
912
        .features[FEAT_1_EDX] =
913
            CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
914 915 916 917
            CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
            CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
            CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
            CPUID_DE | CPUID_FP87,
918
        .features[FEAT_1_ECX] =
919
            CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
920
        .features[FEAT_8000_0001_EDX] =
921
            CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
922
        .features[FEAT_8000_0001_ECX] =
923
            CPUID_EXT3_LAHF_LM,
924 925 926 927 928
        .xlevel = 0x8000000A,
        .model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)",
    },
    {
        .name = "Penryn",
929
        .level = 4,
930
        .vendor = CPUID_VENDOR_INTEL,
931
        .family = 6,
932
        .model = 23,
933
        .stepping = 3,
934
        .features[FEAT_1_EDX] =
935
            CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
936 937 938 939
            CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
            CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
            CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
            CPUID_DE | CPUID_FP87,
940
        .features[FEAT_1_ECX] =
941
            CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
942
            CPUID_EXT_SSE3,
943
        .features[FEAT_8000_0001_EDX] =
944
            CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
945
        .features[FEAT_8000_0001_ECX] =
946
            CPUID_EXT3_LAHF_LM,
947 948 949 950 951
        .xlevel = 0x8000000A,
        .model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)",
    },
    {
        .name = "Nehalem",
952
        .level = 4,
953
        .vendor = CPUID_VENDOR_INTEL,
954
        .family = 6,
955
        .model = 26,
956
        .stepping = 3,
957
        .features[FEAT_1_EDX] =
958
            CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
959 960 961 962
            CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
            CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
            CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
            CPUID_DE | CPUID_FP87,
963
        .features[FEAT_1_ECX] =
964
            CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
965
            CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
966
        .features[FEAT_8000_0001_EDX] =
967
            CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
968
        .features[FEAT_8000_0001_ECX] =
969
            CPUID_EXT3_LAHF_LM,
970 971 972 973 974 975
        .xlevel = 0x8000000A,
        .model_id = "Intel Core i7 9xx (Nehalem Class Core i7)",
    },
    {
        .name = "Westmere",
        .level = 11,
976
        .vendor = CPUID_VENDOR_INTEL,
977 978 979
        .family = 6,
        .model = 44,
        .stepping = 1,
980
        .features[FEAT_1_EDX] =
981
            CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
982 983 984 985
            CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
            CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
            CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
            CPUID_DE | CPUID_FP87,
986
        .features[FEAT_1_ECX] =
987
            CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
988 989
            CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
            CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
990
        .features[FEAT_8000_0001_EDX] =
991
            CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
992
        .features[FEAT_8000_0001_ECX] =
993
            CPUID_EXT3_LAHF_LM,
994 995 996 997 998 999
        .xlevel = 0x8000000A,
        .model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)",
    },
    {
        .name = "SandyBridge",
        .level = 0xd,
1000
        .vendor = CPUID_VENDOR_INTEL,
1001 1002 1003
        .family = 6,
        .model = 42,
        .stepping = 1,
1004
        .features[FEAT_1_EDX] =
1005
            CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1006 1007 1008 1009
            CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
            CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
            CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
            CPUID_DE | CPUID_FP87,
1010
        .features[FEAT_1_ECX] =
1011
            CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1012 1013 1014 1015
            CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
            CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
            CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
            CPUID_EXT_SSE3,
1016
        .features[FEAT_8000_0001_EDX] =
1017
            CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1018
            CPUID_EXT2_SYSCALL,
1019
        .features[FEAT_8000_0001_ECX] =
1020
            CPUID_EXT3_LAHF_LM,
1021 1022 1023
        .xlevel = 0x8000000A,
        .model_id = "Intel Xeon E312xx (Sandy Bridge)",
    },
1024 1025 1026
    {
        .name = "Haswell",
        .level = 0xd,
1027
        .vendor = CPUID_VENDOR_INTEL,
1028 1029 1030
        .family = 6,
        .model = 60,
        .stepping = 1,
1031
        .features[FEAT_1_EDX] =
1032
            CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1033 1034 1035 1036
            CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
            CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
            CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
            CPUID_DE | CPUID_FP87,
1037
        .features[FEAT_1_ECX] =
1038
            CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1039 1040 1041 1042 1043
            CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
            CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
            CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
            CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
            CPUID_EXT_PCID,
1044
        .features[FEAT_8000_0001_EDX] =
1045
            CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1046
            CPUID_EXT2_SYSCALL,
1047
        .features[FEAT_8000_0001_ECX] =
1048
            CPUID_EXT3_LAHF_LM,
1049
        .features[FEAT_7_0_EBX] =
1050
            CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1051 1052 1053 1054 1055 1056
            CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
            CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
            CPUID_7_0_EBX_RTM,
        .xlevel = 0x8000000A,
        .model_id = "Intel Core Processor (Haswell)",
    },
1057 1058 1059 1060 1061 1062 1063 1064 1065 1066 1067 1068 1069 1070 1071 1072 1073 1074 1075 1076 1077 1078 1079 1080 1081 1082 1083 1084 1085 1086 1087 1088 1089 1090
    {
        .name = "Broadwell",
        .level = 0xd,
        .vendor = CPUID_VENDOR_INTEL,
        .family = 6,
        .model = 61,
        .stepping = 2,
        .features[FEAT_1_EDX] =
            CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
            CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
            CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
            CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
            CPUID_DE | CPUID_FP87,
        .features[FEAT_1_ECX] =
            CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
            CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
            CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
            CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
            CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
            CPUID_EXT_PCID,
        .features[FEAT_8000_0001_EDX] =
            CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
            CPUID_EXT2_SYSCALL,
        .features[FEAT_8000_0001_ECX] =
            CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
        .features[FEAT_7_0_EBX] =
            CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
            CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
            CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
            CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
            CPUID_7_0_EBX_SMAP,
        .xlevel = 0x8000000A,
        .model_id = "Intel Core Processor (Broadwell)",
    },
1091 1092 1093
    {
        .name = "Opteron_G1",
        .level = 5,
1094
        .vendor = CPUID_VENDOR_AMD,
1095 1096 1097
        .family = 15,
        .model = 6,
        .stepping = 1,
1098
        .features[FEAT_1_EDX] =
1099
            CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1100 1101 1102 1103
            CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
            CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
            CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
            CPUID_DE | CPUID_FP87,
1104
        .features[FEAT_1_ECX] =
1105
            CPUID_EXT_SSE3,
1106
        .features[FEAT_8000_0001_EDX] =
1107
            CPUID_EXT2_LM | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
1108 1109 1110 1111 1112
            CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
            CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
            CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
            CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
            CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
1113 1114 1115 1116 1117 1118
        .xlevel = 0x80000008,
        .model_id = "AMD Opteron 240 (Gen 1 Class Opteron)",
    },
    {
        .name = "Opteron_G2",
        .level = 5,
1119
        .vendor = CPUID_VENDOR_AMD,
1120 1121 1122
        .family = 15,
        .model = 6,
        .stepping = 1,
1123
        .features[FEAT_1_EDX] =
1124
            CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1125 1126 1127 1128
            CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
            CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
            CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
            CPUID_DE | CPUID_FP87,
1129
        .features[FEAT_1_ECX] =
1130
            CPUID_EXT_CX16 | CPUID_EXT_SSE3,
1131
        .features[FEAT_8000_0001_EDX] =
1132
            CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_FXSR |
1133 1134 1135 1136 1137 1138
            CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
            CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA |
            CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL |
            CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE |
            CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE |
            CPUID_EXT2_DE | CPUID_EXT2_FPU,
1139
        .features[FEAT_8000_0001_ECX] =
1140
            CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
1141 1142 1143 1144 1145 1146
        .xlevel = 0x80000008,
        .model_id = "AMD Opteron 22xx (Gen 2 Class Opteron)",
    },
    {
        .name = "Opteron_G3",
        .level = 5,
1147
        .vendor = CPUID_VENDOR_AMD,
1148 1149 1150
        .family = 15,
        .model = 6,
        .stepping = 1,
1151
        .features[FEAT_1_EDX] =
1152
            CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1153 1154 1155 1156
            CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
            CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
            CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
            CPUID_DE | CPUID_FP87,
1157
        .features[FEAT_1_ECX] =
1158
            CPUID_EXT_POPCNT | CPUID_EXT_CX16 | CPUID_EXT_MONITOR |
1159
            CPUID_EXT_SSE3,
1160
        .features[FEAT_8000_0001_EDX] =
1161
            CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_FXSR |
1162 1163 1164 1165 1166 1167
            CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
            CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA |
            CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL |
            CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE |
            CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE |
            CPUID_EXT2_DE | CPUID_EXT2_FPU,
1168
        .features[FEAT_8000_0001_ECX] =
1169
            CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A |
1170
            CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
1171 1172 1173 1174 1175 1176
        .xlevel = 0x80000008,
        .model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)",
    },
    {
        .name = "Opteron_G4",
        .level = 0xd,
1177
        .vendor = CPUID_VENDOR_AMD,
1178 1179 1180
        .family = 21,
        .model = 1,
        .stepping = 2,
1181
        .features[FEAT_1_EDX] =
1182
            CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1183 1184 1185 1186
            CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
            CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
            CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
            CPUID_DE | CPUID_FP87,
1187
        .features[FEAT_1_ECX] =
1188
            CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1189 1190 1191
            CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
            CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
            CPUID_EXT_SSE3,
1192
        .features[FEAT_8000_0001_EDX] =
1193
            CPUID_EXT2_LM | CPUID_EXT2_RDTSCP |
1194 1195 1196 1197 1198 1199
            CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
            CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
            CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
            CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
            CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
            CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
1200
        .features[FEAT_8000_0001_ECX] =
1201
            CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
1202 1203 1204
            CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
            CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
            CPUID_EXT3_LAHF_LM,
1205 1206 1207
        .xlevel = 0x8000001A,
        .model_id = "AMD Opteron 62xx class CPU",
    },
1208 1209 1210
    {
        .name = "Opteron_G5",
        .level = 0xd,
1211
        .vendor = CPUID_VENDOR_AMD,
1212 1213 1214
        .family = 21,
        .model = 2,
        .stepping = 0,
1215
        .features[FEAT_1_EDX] =
1216
            CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1217 1218 1219 1220
            CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
            CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
            CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
            CPUID_DE | CPUID_FP87,
1221
        .features[FEAT_1_ECX] =
1222
            CPUID_EXT_F16C | CPUID_EXT_AVX | CPUID_EXT_XSAVE |
1223 1224 1225
            CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
            CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_FMA |
            CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
1226
        .features[FEAT_8000_0001_EDX] =
1227
            CPUID_EXT2_LM | CPUID_EXT2_RDTSCP |
1228 1229 1230 1231 1232 1233
            CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
            CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
            CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
            CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
            CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
            CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
1234
        .features[FEAT_8000_0001_ECX] =
1235
            CPUID_EXT3_TBM | CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
1236 1237 1238
            CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
            CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
            CPUID_EXT3_LAHF_LM,
1239 1240 1241
        .xlevel = 0x8000001A,
        .model_id = "AMD Opteron 63xx class CPU",
    },
1242 1243
};

1244 1245 1246 1247 1248 1249 1250 1251 1252 1253 1254 1255 1256 1257 1258
/**
 * x86_cpu_compat_set_features:
 * @cpu_model: CPU model name to be changed. If NULL, all CPU models are changed
 * @w: Identifies the feature word to be changed.
 * @feat_add: Feature bits to be added to feature word
 * @feat_remove: Feature bits to be removed from feature word
 *
 * Change CPU model feature bits for compatibility.
 *
 * This function may be used by machine-type compatibility functions
 * to enable or disable feature bits on specific CPU models.
 */
void x86_cpu_compat_set_features(const char *cpu_model, FeatureWord w,
                                 uint32_t feat_add, uint32_t feat_remove)
{
1259
    X86CPUDefinition *def;
1260 1261 1262 1263 1264 1265 1266 1267 1268 1269
    int i;
    for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
        def = &builtin_x86_defs[i];
        if (!cpu_model || !strcmp(cpu_model, def->name)) {
            def->features[w] |= feat_add;
            def->features[w] &= ~feat_remove;
        }
    }
}

1270 1271 1272
static uint32_t x86_cpu_get_supported_feature_word(FeatureWord w,
                                                   bool migratable_only);

1273 1274
#ifdef CONFIG_KVM

1275 1276 1277 1278 1279 1280 1281 1282 1283 1284 1285 1286 1287 1288 1289
static int cpu_x86_fill_model_id(char *str)
{
    uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
    int i;

    for (i = 0; i < 3; i++) {
        host_cpuid(0x80000002 + i, 0, &eax, &ebx, &ecx, &edx);
        memcpy(str + i * 16 +  0, &eax, 4);
        memcpy(str + i * 16 +  4, &ebx, 4);
        memcpy(str + i * 16 +  8, &ecx, 4);
        memcpy(str + i * 16 + 12, &edx, 4);
    }
    return 0;
}

1290 1291
static X86CPUDefinition host_cpudef;

1292
static Property host_x86_cpu_properties[] = {
1293
    DEFINE_PROP_BOOL("migratable", X86CPU, migratable, true),
1294 1295 1296
    DEFINE_PROP_END_OF_LIST()
};

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