translate-all.c 56.2 KB
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/*
 *  Host code generation
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 *
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 *  Copyright (c) 2003 Fabrice Bellard
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
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 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
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 */
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#ifdef _WIN32
#include <windows.h>
#else
#include <sys/types.h>
#include <sys/mman.h>
#endif
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#include <stdarg.h>
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <inttypes.h>

#include "config.h"
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#include "qemu-common.h"
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#define NO_CPU_IO_DEFS
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#include "cpu.h"
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#include "trace.h"
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#include "disas/disas.h"
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#include "tcg.h"
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#if defined(CONFIG_USER_ONLY)
#include "qemu.h"
#if defined(__FreeBSD__) || defined(__FreeBSD_kernel__)
#include <sys/param.h>
#if __FreeBSD_version >= 700104
#define HAVE_KINFO_GETVMMAP
#define sigqueue sigqueue_freebsd  /* avoid redefinition */
#include <sys/time.h>
#include <sys/proc.h>
#include <machine/profile.h>
#define _KERNEL
#include <sys/user.h>
#undef _KERNEL
#undef sigqueue
#include <libutil.h>
#endif
#endif
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#else
#include "exec/address-spaces.h"
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#endif

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#include "exec/cputlb.h"
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#include "translate-all.h"
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#include "qemu/timer.h"
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//#define DEBUG_TB_INVALIDATE
//#define DEBUG_FLUSH
/* make various TB consistency checks */
//#define DEBUG_TB_CHECK

#if !defined(CONFIG_USER_ONLY)
/* TB consistency checks only implemented for usermode emulation.  */
#undef DEBUG_TB_CHECK
#endif

#define SMC_BITMAP_USE_THRESHOLD 10

typedef struct PageDesc {
    /* list of TBs intersecting this ram page */
    TranslationBlock *first_tb;
    /* in order to optimize self modifying code, we count the number
       of lookups we do to a given page to use a bitmap */
    unsigned int code_write_count;
    uint8_t *code_bitmap;
#if defined(CONFIG_USER_ONLY)
    unsigned long flags;
#endif
} PageDesc;

/* In system mode we want L1_MAP to be based on ram offsets,
   while in user mode we want it to be based on virtual addresses.  */
#if !defined(CONFIG_USER_ONLY)
#if HOST_LONG_BITS < TARGET_PHYS_ADDR_SPACE_BITS
# define L1_MAP_ADDR_SPACE_BITS  HOST_LONG_BITS
#else
# define L1_MAP_ADDR_SPACE_BITS  TARGET_PHYS_ADDR_SPACE_BITS
#endif
#else
# define L1_MAP_ADDR_SPACE_BITS  TARGET_VIRT_ADDR_SPACE_BITS
#endif

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/* Size of the L2 (and L3, etc) page tables.  */
#define V_L2_BITS 10
#define V_L2_SIZE (1 << V_L2_BITS)

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/* The bits remaining after N lower levels of page tables.  */
#define V_L1_BITS_REM \
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    ((L1_MAP_ADDR_SPACE_BITS - TARGET_PAGE_BITS) % V_L2_BITS)
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#if V_L1_BITS_REM < 4
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#define V_L1_BITS  (V_L1_BITS_REM + V_L2_BITS)
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#else
#define V_L1_BITS  V_L1_BITS_REM
#endif

#define V_L1_SIZE  ((target_ulong)1 << V_L1_BITS)

#define V_L1_SHIFT (L1_MAP_ADDR_SPACE_BITS - TARGET_PAGE_BITS - V_L1_BITS)

uintptr_t qemu_real_host_page_size;
uintptr_t qemu_host_page_size;
uintptr_t qemu_host_page_mask;

/* This is a multi-level map on the virtual address space.
   The bottom level has pointers to PageDesc.  */
static void *l1_map[V_L1_SIZE];

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/* code generation context */
TCGContext tcg_ctx;
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static void tb_link_page(TranslationBlock *tb, tb_page_addr_t phys_pc,
                         tb_page_addr_t phys_page2);
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static TranslationBlock *tb_find_pc(uintptr_t tc_ptr);
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void cpu_gen_init(void)
{
    tcg_context_init(&tcg_ctx); 
}

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/* return non zero if the very first instruction is invalid so that
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   the virtual CPU can trigger an exception.
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   '*gen_code_size_ptr' contains the size of the generated code (host
   code).
*/
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int cpu_gen_code(CPUArchState *env, TranslationBlock *tb, int *gen_code_size_ptr)
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{
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    TCGContext *s = &tcg_ctx;
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    tcg_insn_unit *gen_code_buf;
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    int gen_code_size;
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#ifdef CONFIG_PROFILER
    int64_t ti;
#endif

#ifdef CONFIG_PROFILER
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    s->tb_count1++; /* includes aborted translations because of
                       exceptions */
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    ti = profile_getclock();
#endif
    tcg_func_start(s);
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    gen_intermediate_code(env, tb);

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    trace_translate_block(tb, tb->pc, tb->tc_ptr);

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    /* generate machine code */
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    gen_code_buf = tb->tc_ptr;
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    tb->tb_next_offset[0] = 0xffff;
    tb->tb_next_offset[1] = 0xffff;
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    s->tb_next_offset = tb->tb_next_offset;
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#ifdef USE_DIRECT_JUMP
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    s->tb_jmp_offset = tb->tb_jmp_offset;
    s->tb_next = NULL;
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#else
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    s->tb_jmp_offset = NULL;
    s->tb_next = tb->tb_next;
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#endif
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#ifdef CONFIG_PROFILER
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    s->tb_count++;
    s->interm_time += profile_getclock() - ti;
    s->code_time -= profile_getclock();
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#endif
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    gen_code_size = tcg_gen_code(s, gen_code_buf);
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    *gen_code_size_ptr = gen_code_size;
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#ifdef CONFIG_PROFILER
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    s->code_time += profile_getclock();
    s->code_in_len += tb->size;
    s->code_out_len += gen_code_size;
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#endif

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#ifdef DEBUG_DISAS
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    if (qemu_loglevel_mask(CPU_LOG_TB_OUT_ASM)) {
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        qemu_log("OUT: [size=%d]\n", gen_code_size);
        log_disas(tb->tc_ptr, gen_code_size);
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        qemu_log("\n");
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        qemu_log_flush();
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    }
#endif
    return 0;
}

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/* The cpu state corresponding to 'searched_pc' is restored.
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 */
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static int cpu_restore_state_from_tb(CPUState *cpu, TranslationBlock *tb,
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                                     uintptr_t searched_pc)
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{
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    CPUArchState *env = cpu->env_ptr;
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    TCGContext *s = &tcg_ctx;
    int j;
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    uintptr_t tc_ptr;
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#ifdef CONFIG_PROFILER
    int64_t ti;
#endif

#ifdef CONFIG_PROFILER
    ti = profile_getclock();
#endif
    tcg_func_start(s);
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    gen_intermediate_code_pc(env, tb);
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    if (use_icount) {
        /* Reset the cycle counter to the start of the block.  */
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        cpu->icount_decr.u16.low += tb->icount;
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        /* Clear the IO flag.  */
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        cpu->can_do_io = 0;
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    }

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    /* find opc index corresponding to search_pc */
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    tc_ptr = (uintptr_t)tb->tc_ptr;
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    if (searched_pc < tc_ptr)
        return -1;
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    s->tb_next_offset = tb->tb_next_offset;
#ifdef USE_DIRECT_JUMP
    s->tb_jmp_offset = tb->tb_jmp_offset;
    s->tb_next = NULL;
#else
    s->tb_jmp_offset = NULL;
    s->tb_next = tb->tb_next;
#endif
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    j = tcg_gen_code_search_pc(s, (tcg_insn_unit *)tc_ptr,
                               searched_pc - tc_ptr);
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    if (j < 0)
        return -1;
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    /* now find start of instruction before */
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    while (s->gen_opc_instr_start[j] == 0) {
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        j--;
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    }
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    cpu->icount_decr.u16.low -= s->gen_opc_icount[j];
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    restore_state_to_opc(env, tb, j);
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#ifdef CONFIG_PROFILER
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    s->restore_time += profile_getclock() - ti;
    s->restore_count++;
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#endif
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    return 0;
}
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bool cpu_restore_state(CPUState *cpu, uintptr_t retaddr)
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{
    TranslationBlock *tb;

    tb = tb_find_pc(retaddr);
    if (tb) {
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        cpu_restore_state_from_tb(cpu, tb, retaddr);
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        return true;
    }
    return false;
}

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#ifdef _WIN32
static inline void map_exec(void *addr, long size)
{
    DWORD old_protect;
    VirtualProtect(addr, size,
                   PAGE_EXECUTE_READWRITE, &old_protect);
}
#else
static inline void map_exec(void *addr, long size)
{
    unsigned long start, end, page_size;

    page_size = getpagesize();
    start = (unsigned long)addr;
    start &= ~(page_size - 1);

    end = (unsigned long)addr + size;
    end += page_size - 1;
    end &= ~(page_size - 1);

    mprotect((void *)start, end - start,
             PROT_READ | PROT_WRITE | PROT_EXEC);
}
#endif

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void page_size_init(void)
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{
    /* NOTE: we can always suppose that qemu_host_page_size >=
       TARGET_PAGE_SIZE */
    qemu_real_host_page_size = getpagesize();
    if (qemu_host_page_size == 0) {
        qemu_host_page_size = qemu_real_host_page_size;
    }
    if (qemu_host_page_size < TARGET_PAGE_SIZE) {
        qemu_host_page_size = TARGET_PAGE_SIZE;
    }
    qemu_host_page_mask = ~(qemu_host_page_size - 1);
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}
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static void page_init(void)
{
    page_size_init();
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#if defined(CONFIG_BSD) && defined(CONFIG_USER_ONLY)
    {
#ifdef HAVE_KINFO_GETVMMAP
        struct kinfo_vmentry *freep;
        int i, cnt;

        freep = kinfo_getvmmap(getpid(), &cnt);
        if (freep) {
            mmap_lock();
            for (i = 0; i < cnt; i++) {
                unsigned long startaddr, endaddr;

                startaddr = freep[i].kve_start;
                endaddr = freep[i].kve_end;
                if (h2g_valid(startaddr)) {
                    startaddr = h2g(startaddr) & TARGET_PAGE_MASK;

                    if (h2g_valid(endaddr)) {
                        endaddr = h2g(endaddr);
                        page_set_flags(startaddr, endaddr, PAGE_RESERVED);
                    } else {
#if TARGET_ABI_BITS <= L1_MAP_ADDR_SPACE_BITS
                        endaddr = ~0ul;
                        page_set_flags(startaddr, endaddr, PAGE_RESERVED);
#endif
                    }
                }
            }
            free(freep);
            mmap_unlock();
        }
#else
        FILE *f;

        last_brk = (unsigned long)sbrk(0);

        f = fopen("/compat/linux/proc/self/maps", "r");
        if (f) {
            mmap_lock();

            do {
                unsigned long startaddr, endaddr;
                int n;

                n = fscanf(f, "%lx-%lx %*[^\n]\n", &startaddr, &endaddr);

                if (n == 2 && h2g_valid(startaddr)) {
                    startaddr = h2g(startaddr) & TARGET_PAGE_MASK;

                    if (h2g_valid(endaddr)) {
                        endaddr = h2g(endaddr);
                    } else {
                        endaddr = ~0ul;
                    }
                    page_set_flags(startaddr, endaddr, PAGE_RESERVED);
                }
            } while (!feof(f));

            fclose(f);
            mmap_unlock();
        }
#endif
    }
#endif
}

static PageDesc *page_find_alloc(tb_page_addr_t index, int alloc)
{
    PageDesc *pd;
    void **lp;
    int i;

#if defined(CONFIG_USER_ONLY)
    /* We can't use g_malloc because it may recurse into a locked mutex. */
# define ALLOC(P, SIZE)                                 \
    do {                                                \
        P = mmap(NULL, SIZE, PROT_READ | PROT_WRITE,    \
                 MAP_PRIVATE | MAP_ANONYMOUS, -1, 0);   \
    } while (0)
#else
# define ALLOC(P, SIZE) \
    do { P = g_malloc0(SIZE); } while (0)
#endif

    /* Level 1.  Always allocated.  */
    lp = l1_map + ((index >> V_L1_SHIFT) & (V_L1_SIZE - 1));

    /* Level 2..N-1.  */
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    for (i = V_L1_SHIFT / V_L2_BITS - 1; i > 0; i--) {
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        void **p = *lp;

        if (p == NULL) {
            if (!alloc) {
                return NULL;
            }
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            ALLOC(p, sizeof(void *) * V_L2_SIZE);
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            *lp = p;
        }

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        lp = p + ((index >> (i * V_L2_BITS)) & (V_L2_SIZE - 1));
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    }

    pd = *lp;
    if (pd == NULL) {
        if (!alloc) {
            return NULL;
        }
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        ALLOC(pd, sizeof(PageDesc) * V_L2_SIZE);
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        *lp = pd;
    }

#undef ALLOC

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    return pd + (index & (V_L2_SIZE - 1));
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}

static inline PageDesc *page_find(tb_page_addr_t index)
{
    return page_find_alloc(index, 0);
}

#if !defined(CONFIG_USER_ONLY)
#define mmap_lock() do { } while (0)
#define mmap_unlock() do { } while (0)
#endif

#if defined(CONFIG_USER_ONLY)
/* Currently it is not recommended to allocate big chunks of data in
   user mode. It will change when a dedicated libc will be used.  */
/* ??? 64-bit hosts ought to have no problem mmaping data outside the
   region in which the guest needs to run.  Revisit this.  */
#define USE_STATIC_CODE_GEN_BUFFER
#endif

/* ??? Should configure for this, not list operating systems here.  */
#if (defined(__linux__) \
    || defined(__FreeBSD__) || defined(__FreeBSD_kernel__) \
    || defined(__DragonFly__) || defined(__OpenBSD__) \
    || defined(__NetBSD__))
# define USE_MMAP
#endif

/* Minimum size of the code gen buffer.  This number is randomly chosen,
   but not so small that we can't have a fair number of TB's live.  */
#define MIN_CODE_GEN_BUFFER_SIZE     (1024u * 1024)

/* Maximum size of the code gen buffer we'd like to use.  Unless otherwise
   indicated, this is constrained by the range of direct branches on the
   host cpu, as used by the TCG implementation of goto_tb.  */
#if defined(__x86_64__)
# define MAX_CODE_GEN_BUFFER_SIZE  (2ul * 1024 * 1024 * 1024)
#elif defined(__sparc__)
# define MAX_CODE_GEN_BUFFER_SIZE  (2ul * 1024 * 1024 * 1024)
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#elif defined(__aarch64__)
# define MAX_CODE_GEN_BUFFER_SIZE  (128ul * 1024 * 1024)
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#elif defined(__arm__)
# define MAX_CODE_GEN_BUFFER_SIZE  (16u * 1024 * 1024)
#elif defined(__s390x__)
  /* We have a +- 4GB range on the branches; leave some slop.  */
# define MAX_CODE_GEN_BUFFER_SIZE  (3ul * 1024 * 1024 * 1024)
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#elif defined(__mips__)
  /* We have a 256MB branch region, but leave room to make sure the
     main executable is also within that region.  */
# define MAX_CODE_GEN_BUFFER_SIZE  (128ul * 1024 * 1024)
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#else
# define MAX_CODE_GEN_BUFFER_SIZE  ((size_t)-1)
#endif

#define DEFAULT_CODE_GEN_BUFFER_SIZE_1 (32u * 1024 * 1024)

#define DEFAULT_CODE_GEN_BUFFER_SIZE \
  (DEFAULT_CODE_GEN_BUFFER_SIZE_1 < MAX_CODE_GEN_BUFFER_SIZE \
   ? DEFAULT_CODE_GEN_BUFFER_SIZE_1 : MAX_CODE_GEN_BUFFER_SIZE)

static inline size_t size_code_gen_buffer(size_t tb_size)
{
    /* Size the buffer.  */
    if (tb_size == 0) {
#ifdef USE_STATIC_CODE_GEN_BUFFER
        tb_size = DEFAULT_CODE_GEN_BUFFER_SIZE;
#else
        /* ??? Needs adjustments.  */
        /* ??? If we relax the requirement that CONFIG_USER_ONLY use the
           static buffer, we could size this on RESERVED_VA, on the text
           segment size of the executable, or continue to use the default.  */
        tb_size = (unsigned long)(ram_size / 4);
#endif
    }
    if (tb_size < MIN_CODE_GEN_BUFFER_SIZE) {
        tb_size = MIN_CODE_GEN_BUFFER_SIZE;
    }
    if (tb_size > MAX_CODE_GEN_BUFFER_SIZE) {
        tb_size = MAX_CODE_GEN_BUFFER_SIZE;
    }
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    tcg_ctx.code_gen_buffer_size = tb_size;
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    return tb_size;
}

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#ifdef __mips__
/* In order to use J and JAL within the code_gen_buffer, we require
   that the buffer not cross a 256MB boundary.  */
static inline bool cross_256mb(void *addr, size_t size)
{
    return ((uintptr_t)addr ^ ((uintptr_t)addr + size)) & 0xf0000000;
}

/* We weren't able to allocate a buffer without crossing that boundary,
   so make do with the larger portion of the buffer that doesn't cross.
   Returns the new base of the buffer, and adjusts code_gen_buffer_size.  */
static inline void *split_cross_256mb(void *buf1, size_t size1)
{
    void *buf2 = (void *)(((uintptr_t)buf1 + size1) & 0xf0000000);
    size_t size2 = buf1 + size1 - buf2;

    size1 = buf2 - buf1;
    if (size1 < size2) {
        size1 = size2;
        buf1 = buf2;
    }

    tcg_ctx.code_gen_buffer_size = size1;
    return buf1;
}
#endif

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#ifdef USE_STATIC_CODE_GEN_BUFFER
static uint8_t static_code_gen_buffer[DEFAULT_CODE_GEN_BUFFER_SIZE]
    __attribute__((aligned(CODE_GEN_ALIGN)));

static inline void *alloc_code_gen_buffer(void)
{
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    void *buf = static_code_gen_buffer;
#ifdef __mips__
    if (cross_256mb(buf, tcg_ctx.code_gen_buffer_size)) {
        buf = split_cross_256mb(buf, tcg_ctx.code_gen_buffer_size);
    }
#endif
    map_exec(buf, tcg_ctx.code_gen_buffer_size);
    return buf;
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}
#elif defined(USE_MMAP)
static inline void *alloc_code_gen_buffer(void)
{
    int flags = MAP_PRIVATE | MAP_ANONYMOUS;
    uintptr_t start = 0;
    void *buf;

    /* Constrain the position of the buffer based on the host cpu.
       Note that these addresses are chosen in concert with the
       addresses assigned in the relevant linker script file.  */
# if defined(__PIE__) || defined(__PIC__)
    /* Don't bother setting a preferred location if we're building
       a position-independent executable.  We're more likely to get
       an address near the main executable if we let the kernel
       choose the address.  */
# elif defined(__x86_64__) && defined(MAP_32BIT)
    /* Force the memory down into low memory with the executable.
       Leave the choice of exact location with the kernel.  */
    flags |= MAP_32BIT;
    /* Cannot expect to map more than 800MB in low memory.  */
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    if (tcg_ctx.code_gen_buffer_size > 800u * 1024 * 1024) {
        tcg_ctx.code_gen_buffer_size = 800u * 1024 * 1024;
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    }
# elif defined(__sparc__)
    start = 0x40000000ul;
# elif defined(__s390x__)
    start = 0x90000000ul;
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# elif defined(__mips__)
    /* ??? We ought to more explicitly manage layout for softmmu too.  */
#  ifdef CONFIG_USER_ONLY
    start = 0x68000000ul;
#  elif _MIPS_SIM == _ABI64
    start = 0x128000000ul;
#  else
    start = 0x08000000ul;
#  endif
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# endif

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    buf = mmap((void *)start, tcg_ctx.code_gen_buffer_size,
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               PROT_WRITE | PROT_READ | PROT_EXEC, flags, -1, 0);
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    if (buf == MAP_FAILED) {
        return NULL;
    }

#ifdef __mips__
    if (cross_256mb(buf, tcg_ctx.code_gen_buffer_size)) {
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        /* Try again, with the original still mapped, to avoid re-acquiring
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           that 256mb crossing.  This time don't specify an address.  */
        size_t size2, size1 = tcg_ctx.code_gen_buffer_size;
        void *buf2 = mmap(NULL, size1, PROT_WRITE | PROT_READ | PROT_EXEC,
                          flags, -1, 0);
        if (buf2 != MAP_FAILED) {
            if (!cross_256mb(buf2, size1)) {
                /* Success!  Use the new buffer.  */
                munmap(buf, size1);
                return buf2;
            }
            /* Failure.  Work with what we had.  */
            munmap(buf2, size1);
        }

        /* Split the original buffer.  Free the smaller half.  */
        buf2 = split_cross_256mb(buf, size1);
        size2 = tcg_ctx.code_gen_buffer_size;
        munmap(buf + (buf == buf2 ? size2 : 0), size1 - size2);
        return buf2;
    }
#endif

    return buf;
624 625 626 627
}
#else
static inline void *alloc_code_gen_buffer(void)
{
628
    void *buf = g_malloc(tcg_ctx.code_gen_buffer_size);
629

630 631 632 633 634 635 636 637 638 639 640 641 642 643 644 645 646
    if (buf == NULL) {
        return NULL;
    }

#ifdef __mips__
    if (cross_256mb(buf, tcg_ctx.code_gen_buffer_size)) {
        void *buf2 = g_malloc(tcg_ctx.code_gen_buffer_size);
        if (buf2 != NULL && !cross_256mb(buf2, size1)) {
            /* Success!  Use the new buffer.  */
            free(buf);
            buf = buf2;
        } else {
            /* Failure.  Work with what we had.  Since this is malloc
               and not mmap, we can't free the other half.  */
            free(buf2);
            buf = split_cross_256mb(buf, tcg_ctx.code_gen_buffer_size);
        }
647
    }
648 649 650
#endif

    map_exec(buf, tcg_ctx.code_gen_buffer_size);
651 652 653 654 655 656
    return buf;
}
#endif /* USE_STATIC_CODE_GEN_BUFFER, USE_MMAP */

static inline void code_gen_alloc(size_t tb_size)
{
657 658 659
    tcg_ctx.code_gen_buffer_size = size_code_gen_buffer(tb_size);
    tcg_ctx.code_gen_buffer = alloc_code_gen_buffer();
    if (tcg_ctx.code_gen_buffer == NULL) {
660 661 662 663
        fprintf(stderr, "Could not allocate dynamic translator buffer\n");
        exit(1);
    }

664 665
    qemu_madvise(tcg_ctx.code_gen_buffer, tcg_ctx.code_gen_buffer_size,
            QEMU_MADV_HUGEPAGE);
666 667 668 669 670 671

    /* Steal room for the prologue at the end of the buffer.  This ensures
       (via the MAX_CODE_GEN_BUFFER_SIZE limits above) that direct branches
       from TB's to the prologue are going to be in range.  It also means
       that we don't need to mark (additional) portions of the data segment
       as executable.  */
672 673 674
    tcg_ctx.code_gen_prologue = tcg_ctx.code_gen_buffer +
            tcg_ctx.code_gen_buffer_size - 1024;
    tcg_ctx.code_gen_buffer_size -= 1024;
675

676
    tcg_ctx.code_gen_buffer_max_size = tcg_ctx.code_gen_buffer_size -
677
        (TCG_MAX_OP_SIZE * OPC_BUF_SIZE);
678 679
    tcg_ctx.code_gen_max_blocks = tcg_ctx.code_gen_buffer_size /
            CODE_GEN_AVG_BLOCK_SIZE;
680 681
    tcg_ctx.tb_ctx.tbs =
            g_malloc(tcg_ctx.code_gen_max_blocks * sizeof(TranslationBlock));
682 683 684 685 686 687 688 689 690
}

/* Must be called before using the QEMU cpus. 'tb_size' is the size
   (in bytes) allocated to the translation buffer. Zero means default
   size. */
void tcg_exec_init(unsigned long tb_size)
{
    cpu_gen_init();
    code_gen_alloc(tb_size);
691 692
    tcg_ctx.code_gen_ptr = tcg_ctx.code_gen_buffer;
    tcg_register_jit(tcg_ctx.code_gen_buffer, tcg_ctx.code_gen_buffer_size);
693 694 695 696 697 698 699 700 701 702
    page_init();
#if !defined(CONFIG_USER_ONLY) || !defined(CONFIG_USE_GUEST_BASE)
    /* There's no guest base to take into account, so go ahead and
       initialize the prologue now.  */
    tcg_prologue_init(&tcg_ctx);
#endif
}

bool tcg_enabled(void)
{
703
    return tcg_ctx.code_gen_buffer != NULL;
704 705 706 707 708 709 710 711
}

/* Allocate a new translation block. Flush the translation buffer if
   too many translation blocks or too much generated code. */
static TranslationBlock *tb_alloc(target_ulong pc)
{
    TranslationBlock *tb;

712
    if (tcg_ctx.tb_ctx.nb_tbs >= tcg_ctx.code_gen_max_blocks ||
713 714
        (tcg_ctx.code_gen_ptr - tcg_ctx.code_gen_buffer) >=
         tcg_ctx.code_gen_buffer_max_size) {
715 716
        return NULL;
    }
717
    tb = &tcg_ctx.tb_ctx.tbs[tcg_ctx.tb_ctx.nb_tbs++];
718 719 720 721 722 723 724 725 726 727
    tb->pc = pc;
    tb->cflags = 0;
    return tb;
}

void tb_free(TranslationBlock *tb)
{
    /* In practice this is mostly used for single use temporary TB
       Ignore the hard cases and just back up if this TB happens to
       be the last one generated.  */
728 729
    if (tcg_ctx.tb_ctx.nb_tbs > 0 &&
            tb == &tcg_ctx.tb_ctx.tbs[tcg_ctx.tb_ctx.nb_tbs - 1]) {
730
        tcg_ctx.code_gen_ptr = tb->tc_ptr;
731
        tcg_ctx.tb_ctx.nb_tbs--;
732 733 734 735 736 737 738 739 740 741 742 743 744 745 746 747 748 749 750 751 752 753 754
    }
}

static inline void invalidate_page_bitmap(PageDesc *p)
{
    if (p->code_bitmap) {
        g_free(p->code_bitmap);
        p->code_bitmap = NULL;
    }
    p->code_write_count = 0;
}

/* Set to NULL all the 'first_tb' fields in all PageDescs. */
static void page_flush_tb_1(int level, void **lp)
{
    int i;

    if (*lp == NULL) {
        return;
    }
    if (level == 0) {
        PageDesc *pd = *lp;

755
        for (i = 0; i < V_L2_SIZE; ++i) {
756 757 758 759 760 761
            pd[i].first_tb = NULL;
            invalidate_page_bitmap(pd + i);
        }
    } else {
        void **pp = *lp;

762
        for (i = 0; i < V_L2_SIZE; ++i) {
763 764 765 766 767 768 769 770 771 772
            page_flush_tb_1(level - 1, pp + i);
        }
    }
}

static void page_flush_tb(void)
{
    int i;

    for (i = 0; i < V_L1_SIZE; i++) {
773
        page_flush_tb_1(V_L1_SHIFT / V_L2_BITS - 1, l1_map + i);
774 775 776 777 778 779 780
    }
}

/* flush all the translation blocks */
/* XXX: tb_flush is currently not thread safe */
void tb_flush(CPUArchState *env1)
{
781
    CPUState *cpu = ENV_GET_CPU(env1);
782 783 784

#if defined(DEBUG_FLUSH)
    printf("qemu: flush code_size=%ld nb_tbs=%d avg_tb_size=%ld\n",
785
           (unsigned long)(tcg_ctx.code_gen_ptr - tcg_ctx.code_gen_buffer),
786
           tcg_ctx.tb_ctx.nb_tbs, tcg_ctx.tb_ctx.nb_tbs > 0 ?
787
           ((unsigned long)(tcg_ctx.code_gen_ptr - tcg_ctx.code_gen_buffer)) /
788
           tcg_ctx.tb_ctx.nb_tbs : 0);
789
#endif
790 791
    if ((unsigned long)(tcg_ctx.code_gen_ptr - tcg_ctx.code_gen_buffer)
        > tcg_ctx.code_gen_buffer_size) {
792
        cpu_abort(cpu, "Internal error: code buffer overflow\n");
793
    }
794
    tcg_ctx.tb_ctx.nb_tbs = 0;
795

796
    CPU_FOREACH(cpu) {
797
        memset(cpu->tb_jmp_cache, 0, sizeof(cpu->tb_jmp_cache));
798 799
    }

800
    memset(tcg_ctx.tb_ctx.tb_phys_hash, 0, sizeof(tcg_ctx.tb_ctx.tb_phys_hash));
801 802
    page_flush_tb();

803
    tcg_ctx.code_gen_ptr = tcg_ctx.code_gen_buffer;
804 805
    /* XXX: flush processor icache at this point if cache flush is
       expensive */
806
    tcg_ctx.tb_ctx.tb_flush_count++;
807 808 809 810 811 812 813 814 815 816 817
}

#ifdef DEBUG_TB_CHECK

static void tb_invalidate_check(target_ulong address)
{
    TranslationBlock *tb;
    int i;

    address &= TARGET_PAGE_MASK;
    for (i = 0; i < CODE_GEN_PHYS_HASH_SIZE; i++) {
818
        for (tb = tb_ctx.tb_phys_hash[i]; tb != NULL; tb = tb->phys_hash_next) {
819 820 821 822 823 824 825 826 827 828 829 830 831 832 833 834 835
            if (!(address + TARGET_PAGE_SIZE <= tb->pc ||
                  address >= tb->pc + tb->size)) {
                printf("ERROR invalidate: address=" TARGET_FMT_lx
                       " PC=%08lx size=%04x\n",
                       address, (long)tb->pc, tb->size);
            }
        }
    }
}

/* verify that all the pages have correct rights for code */
static void tb_page_check(void)
{
    TranslationBlock *tb;
    int i, flags1, flags2;

    for (i = 0; i < CODE_GEN_PHYS_HASH_SIZE; i++) {
836 837
        for (tb = tcg_ctx.tb_ctx.tb_phys_hash[i]; tb != NULL;
                tb = tb->phys_hash_next) {
838 839 840 841 842 843 844 845 846 847 848 849
            flags1 = page_get_flags(tb->pc);
            flags2 = page_get_flags(tb->pc + tb->size - 1);
            if ((flags1 & PAGE_WRITE) || (flags2 & PAGE_WRITE)) {
                printf("ERROR page flags: PC=%08lx size=%04x f1=%x f2=%x\n",
                       (long)tb->pc, tb->size, flags1, flags2);
            }
        }
    }
}

#endif

850
static inline void tb_hash_remove(TranslationBlock **ptb, TranslationBlock *tb)
851 852 853 854 855 856
{
    TranslationBlock *tb1;

    for (;;) {
        tb1 = *ptb;
        if (tb1 == tb) {
857
            *ptb = tb1->phys_hash_next;
858 859
            break;
        }
860
        ptb = &tb1->phys_hash_next;
861 862 863 864 865 866 867 868 869 870 871 872 873 874 875 876 877 878 879 880 881 882 883 884 885 886 887 888 889 890 891 892 893 894 895 896 897 898 899 900 901 902 903 904 905 906 907 908 909 910 911 912 913 914 915 916
    }
}

static inline void tb_page_remove(TranslationBlock **ptb, TranslationBlock *tb)
{
    TranslationBlock *tb1;
    unsigned int n1;

    for (;;) {
        tb1 = *ptb;
        n1 = (uintptr_t)tb1 & 3;
        tb1 = (TranslationBlock *)((uintptr_t)tb1 & ~3);
        if (tb1 == tb) {
            *ptb = tb1->page_next[n1];
            break;
        }
        ptb = &tb1->page_next[n1];
    }
}

static inline void tb_jmp_remove(TranslationBlock *tb, int n)
{
    TranslationBlock *tb1, **ptb;
    unsigned int n1;

    ptb = &tb->jmp_next[n];
    tb1 = *ptb;
    if (tb1) {
        /* find tb(n) in circular list */
        for (;;) {
            tb1 = *ptb;
            n1 = (uintptr_t)tb1 & 3;
            tb1 = (TranslationBlock *)((uintptr_t)tb1 & ~3);
            if (n1 == n && tb1 == tb) {
                break;
            }
            if (n1 == 2) {
                ptb = &tb1->jmp_first;
            } else {
                ptb = &tb1->jmp_next[n1];
            }
        }
        /* now we can suppress tb(n) from the list */
        *ptb = tb->jmp_next[n];

        tb->jmp_next[n] = NULL;
    }
}

/* reset the jump entry 'n' of a TB so that it is not chained to
   another TB */
static inline void tb_reset_jump(TranslationBlock *tb, int n)
{
    tb_set_jmp_target(tb, n, (uintptr_t)(tb->tc_ptr + tb->tb_next_offset[n]));
}

917
/* invalidate one TB */
918 919
void tb_phys_invalidate(TranslationBlock *tb, tb_page_addr_t page_addr)
{
920
    CPUState *cpu;
921 922 923 924 925 926 927 928
    PageDesc *p;
    unsigned int h, n1;
    tb_page_addr_t phys_pc;
    TranslationBlock *tb1, *tb2;

    /* remove the TB from the hash list */
    phys_pc = tb->page_addr[0] + (tb->pc & ~TARGET_PAGE_MASK);
    h = tb_phys_hash_func(phys_pc);
929
    tb_hash_remove(&tcg_ctx.tb_ctx.tb_phys_hash[h], tb);
930 931 932 933 934 935 936 937 938 939 940 941 942

    /* remove the TB from the page list */
    if (tb->page_addr[0] != page_addr) {
        p = page_find(tb->page_addr[0] >> TARGET_PAGE_BITS);
        tb_page_remove(&p->first_tb, tb);
        invalidate_page_bitmap(p);
    }
    if (tb->page_addr[1] != -1 && tb->page_addr[1] != page_addr) {
        p = page_find(tb->page_addr[1] >> TARGET_PAGE_BITS);
        tb_page_remove(&p->first_tb, tb);
        invalidate_page_bitmap(p);
    }

943
    tcg_ctx.tb_ctx.tb_invalidated_flag = 1;
944 945 946

    /* remove the TB from the hash list */
    h = tb_jmp_cache_hash_func(tb->pc);
947
    CPU_FOREACH(cpu) {
948 949
        if (cpu->tb_jmp_cache[h] == tb) {
            cpu->tb_jmp_cache[h] = NULL;
950 951 952 953 954 955 956 957 958 959 960 961 962 963 964 965 966 967 968 969 970 971
        }
    }

    /* suppress this TB from the two jump lists */
    tb_jmp_remove(tb, 0);
    tb_jmp_remove(tb, 1);

    /* suppress any remaining jumps to this TB */
    tb1 = tb->jmp_first;
    for (;;) {
        n1 = (uintptr_t)tb1 & 3;
        if (n1 == 2) {
            break;
        }
        tb1 = (TranslationBlock *)((uintptr_t)tb1 & ~3);
        tb2 = tb1->jmp_next[n1];
        tb_reset_jump(tb1, n1);
        tb1->jmp_next[n1] = NULL;
        tb1 = tb2;
    }
    tb->jmp_first = (TranslationBlock *)((uintptr_t)tb | 2); /* fail safe */

972
    tcg_ctx.tb_ctx.tb_phys_invalidate_count++;
973 974 975 976 977 978 979 980 981 982 983 984 985 986 987 988 989 990 991 992 993 994 995 996 997 998 999 1000 1001 1002 1003 1004 1005 1006 1007 1008 1009 1010 1011 1012 1013 1014 1015 1016 1017 1018 1019 1020 1021 1022 1023 1024 1025 1026 1027 1028 1029 1030
}

static inline void set_bits(uint8_t *tab, int start, int len)
{
    int end, mask, end1;

    end = start + len;
    tab += start >> 3;
    mask = 0xff << (start & 7);
    if ((start & ~7) == (end & ~7)) {
        if (start < end) {
            mask &= ~(0xff << (end & 7));
            *tab |= mask;
        }
    } else {
        *tab++ |= mask;
        start = (start + 8) & ~7;
        end1 = end & ~7;
        while (start < end1) {
            *tab++ = 0xff;
            start += 8;
        }
        if (start < end) {
            mask = ~(0xff << (end & 7));
            *tab |= mask;
        }
    }
}

static void build_page_bitmap(PageDesc *p)
{
    int n, tb_start, tb_end;
    TranslationBlock *tb;

    p->code_bitmap = g_malloc0(TARGET_PAGE_SIZE / 8);

    tb = p->first_tb;
    while (tb != NULL) {
        n = (uintptr_t)tb & 3;
        tb = (TranslationBlock *)((uintptr_t)tb & ~3);
        /* NOTE: this is subtle as a TB may span two physical pages */
        if (n == 0) {
            /* NOTE: tb_end may be after the end of the page, but
               it is not a problem */
            tb_start = tb->pc & ~TARGET_PAGE_MASK;
            tb_end = tb_start + tb->size;
            if (tb_end > TARGET_PAGE_SIZE) {
                tb_end = TARGET_PAGE_SIZE;
            }
        } else {
            tb_start = 0;
            tb_end = ((tb->pc + tb->size) & ~TARGET_PAGE_MASK);
        }
        set_bits(p->code_bitmap, tb_start, tb_end - tb_start);
        tb = tb->page_next[n];
    }
}

1031
TranslationBlock *tb_gen_code(CPUState *cpu,
1032 1033 1034
                              target_ulong pc, target_ulong cs_base,
                              int flags, int cflags)
{
1035
    CPUArchState *env = cpu->env_ptr;
1036 1037 1038 1039 1040 1041 1042 1043 1044 1045 1046 1047 1048
    TranslationBlock *tb;
    tb_page_addr_t phys_pc, phys_page2;
    target_ulong virt_page2;
    int code_gen_size;

    phys_pc = get_page_addr_code(env, pc);
    tb = tb_alloc(pc);
    if (!tb) {
        /* flush must be done */
        tb_flush(env);
        /* cannot fail at this point */
        tb = tb_alloc(pc);
        /* Don't forget to invalidate previous TB info.  */
1049
        tcg_ctx.tb_ctx.tb_invalidated_flag = 1;
1050
    }
1051
    tb->tc_ptr = tcg_ctx.code_gen_ptr;
1052 1053 1054 1055
    tb->cs_base = cs_base;
    tb->flags = flags;
    tb->cflags = cflags;
    cpu_gen_code(env, tb, &code_gen_size);
1056 1057
    tcg_ctx.code_gen_ptr = (void *)(((uintptr_t)tcg_ctx.code_gen_ptr +
            code_gen_size + CODE_GEN_ALIGN - 1) & ~(CODE_GEN_ALIGN - 1));
1058 1059 1060 1061 1062 1063 1064 1065 1066 1067 1068 1069 1070 1071 1072 1073 1074 1075 1076 1077 1078 1079 1080 1081 1082 1083 1084 1085 1086 1087 1088 1089 1090 1091 1092 1093 1094 1095 1096

    /* check next page if needed */
    virt_page2 = (pc + tb->size - 1) & TARGET_PAGE_MASK;
    phys_page2 = -1;
    if ((pc & TARGET_PAGE_MASK) != virt_page2) {
        phys_page2 = get_page_addr_code(env, virt_page2);
    }
    tb_link_page(tb, phys_pc, phys_page2);
    return tb;
}

/*
 * Invalidate all TBs which intersect with the target physical address range
 * [start;end[. NOTE: start and end may refer to *different* physical pages.
 * 'is_cpu_write_access' should be true if called from a real cpu write
 * access: the virtual CPU will exit the current TB if code is modified inside
 * this TB.
 */
void tb_invalidate_phys_range(tb_page_addr_t start, tb_page_addr_t end,
                              int is_cpu_write_access)
{
    while (start < end) {
        tb_invalidate_phys_page_range(start, end, is_cpu_write_access);
        start &= TARGET_PAGE_MASK;
        start += TARGET_PAGE_SIZE;
    }
}

/*
 * Invalidate all TBs which intersect with the target physical address range
 * [start;end[. NOTE: start and end must refer to the *same* physical page.
 * 'is_cpu_write_access' should be true if called from a real cpu write
 * access: the virtual CPU will exit the current TB if code is modified inside
 * this TB.
 */
void tb_invalidate_phys_page_range(tb_page_addr_t start, tb_page_addr_t end,
                                   int is_cpu_write_access)
{
    TranslationBlock *tb, *tb_next, *saved_tb;
1097
    CPUState *cpu = current_cpu;
1098
#if defined(TARGET_HAS_PRECISE_SMC)
1099 1100
    CPUArchState *env = NULL;
#endif
1101 1102 1103 1104 1105 1106 1107 1108 1109 1110 1111 1112 1113 1114 1115 1116 1117 1118 1119 1120 1121 1122
    tb_page_addr_t tb_start, tb_end;
    PageDesc *p;
    int n;
#ifdef TARGET_HAS_PRECISE_SMC
    int current_tb_not_found = is_cpu_write_access;
    TranslationBlock *current_tb = NULL;
    int current_tb_modified = 0;
    target_ulong current_pc = 0;
    target_ulong current_cs_base = 0;
    int current_flags = 0;
#endif /* TARGET_HAS_PRECISE_SMC */

    p = page_find(start >> TARGET_PAGE_BITS);
    if (!p) {
        return;
    }
    if (!p->code_bitmap &&
        ++p->code_write_count >= SMC_BITMAP_USE_THRESHOLD &&
        is_cpu_write_access) {
        /* build code bitmap */
        build_page_bitmap(p);
    }
1123
#if defined(TARGET_HAS_PRECISE_SMC)
1124 1125
    if (cpu != NULL) {
        env = cpu->env_ptr;
1126
    }
1127
#endif
1128 1129 1130 1131 1132 1133 1134 1135 1136 1137 1138 1139 1140 1141 1142 1143 1144 1145 1146 1147 1148 1149 1150 1151

    /* we remove all the TBs in the range [start, end[ */
    /* XXX: see if in some cases it could be faster to invalidate all
       the code */
    tb = p->first_tb;
    while (tb != NULL) {
        n = (uintptr_t)tb & 3;
        tb = (TranslationBlock *)((uintptr_t)tb & ~3);
        tb_next = tb->page_next[n];
        /* NOTE: this is subtle as a TB may span two physical pages */
        if (n == 0) {
            /* NOTE: tb_end may be after the end of the page, but
               it is not a problem */
            tb_start = tb->page_addr[0] + (tb->pc & ~TARGET_PAGE_MASK);
            tb_end = tb_start + tb->size;
        } else {
            tb_start = tb->page_addr[1];
            tb_end = tb_start + ((tb->pc + tb->size) & ~TARGET_PAGE_MASK);
        }
        if (!(tb_end <= start || tb_start >= end)) {
#ifdef TARGET_HAS_PRECISE_SMC
            if (current_tb_not_found) {
                current_tb_not_found = 0;
                current_tb = NULL;
1152
                if (cpu->mem_io_pc) {
1153
                    /* now we have a real cpu fault */
1154
                    current_tb = tb_find_pc(cpu->mem_io_pc);
1155 1156 1157 1158 1159 1160 1161 1162 1163 1164 1165
                }
            }
            if (current_tb == tb &&
                (current_tb->cflags & CF_COUNT_MASK) != 1) {
                /* If we are modifying the current TB, we must stop
                its execution. We could be more precise by checking
                that the modification is after the current PC, but it
                would require a specialized function to partially
                restore the CPU state */

                current_tb_modified = 1;
1166
                cpu_restore_state_from_tb(cpu, current_tb, cpu->mem_io_pc);
1167 1168 1169 1170 1171 1172 1173
                cpu_get_tb_cpu_state(env, &current_pc, &current_cs_base,
                                     &current_flags);
            }
#endif /* TARGET_HAS_PRECISE_SMC */
            /* we need to do that to handle the case where a signal
               occurs while doing tb_phys_invalidate() */
            saved_tb = NULL;
1174 1175 1176
            if (cpu != NULL) {
                saved_tb = cpu->current_tb;
                cpu->current_tb = NULL;
1177 1178
            }
            tb_phys_invalidate(tb, -1);
1179 1180
            if (cpu != NULL) {
                cpu->current_tb = saved_tb;
1181 1182
                if (cpu->interrupt_request && cpu->current_tb) {
                    cpu_interrupt(cpu, cpu->interrupt_request);
1183 1184 1185 1186 1187 1188 1189 1190 1191 1192
                }
            }
        }
        tb = tb_next;
    }
#if !defined(CONFIG_USER_ONLY)
    /* if no code remaining, no need to continue to use slow writes */
    if (!p->first_tb) {
        invalidate_page_bitmap(p);
        if (is_cpu_write_access) {
1193
            tlb_unprotect_code_phys(cpu, start, cpu->mem_io_vaddr);
1194 1195 1196 1197 1198 1199 1200 1201
        }
    }
#endif
#ifdef TARGET_HAS_PRECISE_SMC
    if (current_tb_modified) {
        /* we generate a block containing just the instruction
           modifying the memory. It will ensure that it cannot modify
           itself */
1202
        cpu->current_tb = NULL;
1203
        tb_gen_code(cpu, current_pc, current_cs_base, current_flags, 1);
1204
        cpu_resume_from_signal(cpu, NULL);
1205 1206 1207 1208 1209 1210 1211 1212 1213 1214 1215 1216 1217 1218 1219 1220 1221 1222 1223 1224 1225 1226 1227 1228 1229 1230 1231 1232 1233 1234 1235 1236 1237 1238 1239 1240 1241
    }
#endif
}

/* len must be <= 8 and start must be a multiple of len */
void tb_invalidate_phys_page_fast(tb_page_addr_t start, int len)
{
    PageDesc *p;
    int offset, b;

#if 0
    if (1) {
        qemu_log("modifying code at 0x%x size=%d EIP=%x PC=%08x\n",
                  cpu_single_env->mem_io_vaddr, len,
                  cpu_single_env->eip,
                  cpu_single_env->eip +
                  (intptr_t)cpu_single_env->segs[R_CS].base);
    }
#endif
    p = page_find(start >> TARGET_PAGE_BITS);
    if (!p) {
        return;
    }
    if (p->code_bitmap) {
        offset = start & ~TARGET_PAGE_MASK;
        b = p->code_bitmap[offset >> 3] >> (offset & 7);
        if (b & ((1 << len) - 1)) {
            goto do_invalidate;
        }
    } else {
    do_invalidate:
        tb_invalidate_phys_page_range(start, start + len, 1);
    }
}

#if !defined(CONFIG_SOFTMMU)
static void tb_invalidate_phys_page(tb_page_addr_t addr,
1242 1243
                                    uintptr_t pc, void *puc,
                                    bool locked)
1244 1245 1246 1247 1248 1249
{
    TranslationBlock *tb;
    PageDesc *p;
    int n;
#ifdef TARGET_HAS_PRECISE_SMC
    TranslationBlock *current_tb = NULL;
1250 1251
    CPUState *cpu = current_cpu;
    CPUArchState *env = NULL;
1252 1253 1254 1255 1256 1257 1258 1259 1260 1261 1262 1263 1264 1265 1266 1267
    int current_tb_modified = 0;
    target_ulong current_pc = 0;
    target_ulong current_cs_base = 0;
    int current_flags = 0;
#endif

    addr &= TARGET_PAGE_MASK;
    p = page_find(addr >> TARGET_PAGE_BITS);
    if (!p) {
        return;
    }
    tb = p->first_tb;
#ifdef TARGET_HAS_PRECISE_SMC
    if (tb && pc != 0) {
        current_tb = tb_find_pc(pc);
    }
1268 1269
    if (cpu != NULL) {
        env = cpu->env_ptr;
1270
    }
1271 1272 1273 1274 1275 1276 1277 1278 1279 1280 1281 1282 1283 1284
#endif
    while (tb != NULL) {
        n = (uintptr_t)tb & 3;
        tb = (TranslationBlock *)((uintptr_t)tb & ~3);
#ifdef TARGET_HAS_PRECISE_SMC
        if (current_tb == tb &&
            (current_tb->cflags & CF_COUNT_MASK) != 1) {
                /* If we are modifying the current TB, we must stop
                   its execution. We could be more precise by checking
                   that the modification is after the current PC, but it
                   would require a specialized function to partially
                   restore the CPU state */

            current_tb_modified = 1;
1285
            cpu_restore_state_from_tb(cpu, current_tb, pc);
1286 1287 1288 1289 1290 1291 1292 1293 1294 1295 1296 1297 1298
            cpu_get_tb_cpu_state(env, &current_pc, &current_cs_base,
                                 &current_flags);
        }
#endif /* TARGET_HAS_PRECISE_SMC */
        tb_phys_invalidate(tb, addr);
        tb = tb->page_next[n];
    }
    p->first_tb = NULL;
#ifdef TARGET_HAS_PRECISE_SMC
    if (current_tb_modified) {
        /* we generate a block containing just the instruction
           modifying the memory. It will ensure that it cannot modify
           itself */
1299
        cpu->current_tb = NULL;
1300
        tb_gen_code(cpu, current_pc, current_cs_base, current_flags, 1);
1301 1302 1303
        if (locked) {
            mmap_unlock();
        }
1304
        cpu_resume_from_signal(cpu, puc);
1305 1306 1307 1308 1309 1310 1311 1312 1313 1314 1315 1316 1317 1318 1319 1320 1321 1322 1323 1324 1325 1326 1327 1328 1329 1330 1331 1332 1333 1334 1335 1336 1337 1338 1339 1340 1341 1342 1343 1344 1345 1346 1347 1348 1349 1350 1351 1352 1353 1354 1355 1356 1357 1358 1359 1360 1361 1362 1363 1364 1365 1366 1367 1368 1369 1370 1371 1372 1373 1374 1375 1376 1377 1378 1379 1380 1381
    }
#endif
}
#endif

/* add the tb in the target page and protect it if necessary */
static inline void tb_alloc_page(TranslationBlock *tb,
                                 unsigned int n, tb_page_addr_t page_addr)
{
    PageDesc *p;
#ifndef CONFIG_USER_ONLY
    bool page_already_protected;
#endif

    tb->page_addr[n] = page_addr;
    p = page_find_alloc(page_addr >> TARGET_PAGE_BITS, 1);
    tb->page_next[n] = p->first_tb;
#ifndef CONFIG_USER_ONLY
    page_already_protected = p->first_tb != NULL;
#endif
    p->first_tb = (TranslationBlock *)((uintptr_t)tb | n);
    invalidate_page_bitmap(p);

#if defined(TARGET_HAS_SMC) || 1

#if defined(CONFIG_USER_ONLY)
    if (p->flags & PAGE_WRITE) {
        target_ulong addr;
        PageDesc *p2;
        int prot;

        /* force the host page as non writable (writes will have a
           page fault + mprotect overhead) */
        page_addr &= qemu_host_page_mask;
        prot = 0;
        for (addr = page_addr; addr < page_addr + qemu_host_page_size;
            addr += TARGET_PAGE_SIZE) {

            p2 = page_find(addr >> TARGET_PAGE_BITS);
            if (!p2) {
                continue;
            }
            prot |= p2->flags;
            p2->flags &= ~PAGE_WRITE;
          }
        mprotect(g2h(page_addr), qemu_host_page_size,
                 (prot & PAGE_BITS) & ~PAGE_WRITE);
#ifdef DEBUG_TB_INVALIDATE
        printf("protecting code page: 0x" TARGET_FMT_lx "\n",
               page_addr);
#endif
    }
#else
    /* if some code is already present, then the pages are already
       protected. So we handle the case where only the first TB is
       allocated in a physical page */
    if (!page_already_protected) {
        tlb_protect_code(page_addr);
    }
#endif

#endif /* TARGET_HAS_SMC */
}

/* add a new TB and link it to the physical page tables. phys_page2 is
   (-1) to indicate that only one page contains the TB. */
static void tb_link_page(TranslationBlock *tb, tb_page_addr_t phys_pc,
                         tb_page_addr_t phys_page2)
{
    unsigned int h;
    TranslationBlock **ptb;

    /* Grab the mmap lock to stop another thread invalidating this TB
       before we are done.  */
    mmap_lock();
    /* add in the physical hash table */
    h = tb_phys_hash_func(phys_pc);
1382
    ptb = &tcg_ctx.tb_ctx.tb_phys_hash[h];
1383 1384 1385 1386 1387 1388 1389 1390 1391 1392 1393 1394 1395 1396 1397 1398 1399 1400 1401 1402 1403 1404 1405 1406 1407 1408 1409 1410 1411 1412 1413
    tb->phys_hash_next = *ptb;
    *ptb = tb;

    /* add in the page list */
    tb_alloc_page(tb, 0, phys_pc & TARGET_PAGE_MASK);
    if (phys_page2 != -1) {
        tb_alloc_page(tb, 1, phys_page2);
    } else {
        tb->page_addr[1] = -1;
    }

    tb->jmp_first = (TranslationBlock *)((uintptr_t)tb | 2);
    tb->jmp_next[0] = NULL;
    tb->jmp_next[1] = NULL;

    /* init original jump addresses */
    if (tb->tb_next_offset[0] != 0xffff) {
        tb_reset_jump(tb, 0);
    }
    if (tb->tb_next_offset[1] != 0xffff) {
        tb_reset_jump(tb, 1);
    }

#ifdef DEBUG_TB_CHECK
    tb_page_check();
#endif
    mmap_unlock();
}

/* find the TB 'tb' such that tb[0].tc_ptr <= tc_ptr <
   tb[1].tc_ptr. Return NULL if not found */
1414
static TranslationBlock *tb_find_pc(uintptr_t tc_ptr)
1415 1416 1417 1418 1419
{
    int m_min, m_max, m;
    uintptr_t v;
    TranslationBlock *tb;

1420
    if (tcg_ctx.tb_ctx.nb_tbs <= 0) {
1421 1422
        return NULL;
    }
1423 1424
    if (tc_ptr < (uintptr_t)tcg_ctx.code_gen_buffer ||
        tc_ptr >= (uintptr_t)tcg_ctx.code_gen_ptr) {
1425 1426 1427 1428
        return NULL;
    }
    /* binary search (cf Knuth) */
    m_min = 0;
1429
    m_max = tcg_ctx.tb_ctx.nb_tbs - 1;
1430 1431
    while (m_min <= m_max) {
        m = (m_min + m_max) >> 1;
1432
        tb = &tcg_ctx.tb_ctx.tbs[m];
1433 1434 1435 1436 1437 1438 1439 1440 1441
        v = (uintptr_t)tb->tc_ptr;
        if (v == tc_ptr) {
            return tb;
        } else if (tc_ptr < v) {
            m_max = m - 1;
        } else {
            m_min = m + 1;
        }
    }
1442
    return &tcg_ctx.tb_ctx.tbs[m_max];
1443 1444 1445
}

#if defined(TARGET_HAS_ICE) && !defined(CONFIG_USER_ONLY)
1446
void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr)
1447 1448
{
    ram_addr_t ram_addr;
1449
    MemoryRegion *mr;
1450
    hwaddr l = 1;
1451

1452
    mr = address_space_translate(as, addr, &addr, &l, false);
1453 1454
    if (!(memory_region_is_ram(mr)
          || memory_region_is_romd(mr))) {
1455 1456
        return;
    }
1457
    ram_addr = (memory_region_get_ram_addr(mr) & TARGET_PAGE_MASK)
1458
        + addr;
1459 1460 1461 1462
    tb_invalidate_phys_page_range(ram_addr, ram_addr + 1, 0);
}
#endif /* TARGET_HAS_ICE && !defined(CONFIG_USER_ONLY) */

1463
void tb_check_watchpoint(CPUState *cpu)
1464 1465 1466
{
    TranslationBlock *tb;

1467
    tb = tb_find_pc(cpu->mem_io_pc);
1468
    if (!tb) {
1469
        cpu_abort(cpu, "check_watchpoint: could not find TB for pc=%p",
1470
                  (void *)cpu->mem_io_pc);
1471
    }
1472
    cpu_restore_state_from_tb(cpu, tb, cpu->mem_io_pc);
1473 1474 1475 1476 1477
    tb_phys_invalidate(tb, -1);
}

#ifndef CONFIG_USER_ONLY
/* mask must never be zero, except for A20 change call */
1478
static void tcg_handle_interrupt(CPUState *cpu, int mask)
1479 1480 1481
{
    int old_mask;

1482 1483
    old_mask = cpu->interrupt_request;
    cpu->interrupt_request |= mask;
1484 1485 1486 1487 1488 1489 1490 1491 1492 1493 1494

    /*
     * If called from iothread context, wake the target cpu in
     * case its halted.
     */
    if (!qemu_cpu_is_self(cpu)) {
        qemu_cpu_kick(cpu);
        return;
    }

    if (use_icount) {
1495
        cpu->icount_decr.u16.high = 0xffff;
1496
        if (!cpu_can_do_io(cpu)
1497
            && (mask & ~old_mask) != 0) {
1498
            cpu_abort(cpu, "Raised interrupt while not in I/O function");
1499 1500
        }
    } else {
1501
        cpu->tcg_exit_req = 1;
1502 1503 1504 1505 1506 1507 1508
    }
}

CPUInterruptHandler cpu_interrupt_handler = tcg_handle_interrupt;

/* in deterministic execution mode, instructions doing device I/Os
   must be at the end of the TB */
1509
void cpu_io_recompile(CPUState *cpu, uintptr_t retaddr)
1510
{
1511
#if defined(TARGET_MIPS) || defined(TARGET_SH4)
1512
    CPUArchState *env = cpu->env_ptr;
1513
#endif
1514 1515 1516 1517 1518 1519 1520
    TranslationBlock *tb;
    uint32_t n, cflags;
    target_ulong pc, cs_base;
    uint64_t flags;

    tb = tb_find_pc(retaddr);
    if (!tb) {
1521
        cpu_abort(cpu, "cpu_io_recompile: could not find TB for pc=%p",
1522 1523
                  (void *)retaddr);
    }
1524
    n = cpu->icount_decr.u16.low + tb->icount;
1525
    cpu_restore_state_from_tb(cpu, tb, retaddr);
1526 1527
    /* Calculate how many instructions had been executed before the fault
       occurred.  */
1528
    n = n - cpu->icount_decr.u16.low;
1529 1530 1531 1532 1533 1534 1535 1536 1537
    /* Generate a new TB ending on the I/O insn.  */
    n++;
    /* On MIPS and SH, delay slot instructions can only be restarted if
       they were already the first instruction in the TB.  If this is not
       the first instruction in a TB then re-execute the preceding
       branch.  */
#if defined(TARGET_MIPS)
    if ((env->hflags & MIPS_HFLAG_BMASK) != 0 && n > 1) {
        env->active_tc.PC -= 4;
1538
        cpu->icount_decr.u16.low++;
1539 1540 1541 1542 1543 1544
        env->hflags &= ~MIPS_HFLAG_BMASK;
    }
#elif defined(TARGET_SH4)
    if ((env->flags & ((DELAY_SLOT | DELAY_SLOT_CONDITIONAL))) != 0
            && n > 1) {
        env->pc -= 2;
1545
        cpu->icount_decr.u16.low++;
1546 1547 1548 1549 1550
        env->flags &= ~(DELAY_SLOT | DELAY_SLOT_CONDITIONAL);
    }
#endif
    /* This should never happen.  */
    if (n > CF_COUNT_MASK) {
1551
        cpu_abort(cpu, "TB too big during recompile");
1552 1553 1554 1555 1556 1557 1558 1559 1560
    }

    cflags = n | CF_LAST_IO;
    pc = tb->pc;
    cs_base = tb->cs_base;
    flags = tb->flags;
    tb_phys_invalidate(tb, -1);
    /* FIXME: In theory this could raise an exception.  In practice
       we have already translated the block once so it's probably ok.  */
1561
    tb_gen_code(cpu, pc, cs_base, flags, cflags);
1562 1563 1564 1565 1566
    /* TODO: If env->pc != tb->pc (i.e. the faulting instruction was not
       the first in the TB) then we end up generating a whole new TB and
       repeating the fault, which is horribly inefficient.
       Better would be to execute just this insn uncached, or generate a
       second new TB.  */
1567
    cpu_resume_from_signal(cpu, NULL);
1568 1569
}

1570
void tb_flush_jmp_cache(CPUState *cpu, target_ulong addr)
1571 1572 1573 1574 1575 1576
{
    unsigned int i;

    /* Discard jump cache entries for any tb which might potentially
       overlap the flushed page.  */
    i = tb_jmp_cache_hash_page(addr - TARGET_PAGE_SIZE);
1577
    memset(&cpu->tb_jmp_cache[i], 0,
1578 1579 1580
           TB_JMP_PAGE_SIZE * sizeof(TranslationBlock *));

    i = tb_jmp_cache_hash_page(addr);
1581
    memset(&cpu->tb_jmp_cache[i], 0,
1582 1583 1584 1585 1586 1587 1588 1589 1590 1591 1592 1593 1594 1595
           TB_JMP_PAGE_SIZE * sizeof(TranslationBlock *));
}

void dump_exec_info(FILE *f, fprintf_function cpu_fprintf)
{
    int i, target_code_size, max_target_code_size;
    int direct_jmp_count, direct_jmp2_count, cross_page;
    TranslationBlock *tb;

    target_code_size = 0;
    max_target_code_size = 0;
    cross_page = 0;
    direct_jmp_count = 0;
    direct_jmp2_count = 0;
1596 1597
    for (i = 0; i < tcg_ctx.tb_ctx.nb_tbs; i++) {
        tb = &tcg_ctx.tb_ctx.tbs[i];
1598 1599 1600 1601 1602 1603 1604 1605 1606 1607 1608 1609 1610 1611 1612 1613 1614
        target_code_size += tb->size;
        if (tb->size > max_target_code_size) {
            max_target_code_size = tb->size;
        }
        if (tb->page_addr[1] != -1) {
            cross_page++;
        }
        if (tb->tb_next_offset[0] != 0xffff) {
            direct_jmp_count++;
            if (tb->tb_next_offset[1] != 0xffff) {
                direct_jmp2_count++;
            }
        }
    }
    /* XXX: avoid using doubles ? */
    cpu_fprintf(f, "Translation buffer state:\n");
    cpu_fprintf(f, "gen code size       %td/%zd\n",
1615 1616
                tcg_ctx.code_gen_ptr - tcg_ctx.code_gen_buffer,
                tcg_ctx.code_gen_buffer_max_size);
1617
    cpu_fprintf(f, "TB count            %d/%d\n",
1618
            tcg_ctx.tb_ctx.nb_tbs, tcg_ctx.code_gen_max_blocks);
1619
    cpu_fprintf(f, "TB avg target size  %d max=%d bytes\n",
1620 1621 1622
            tcg_ctx.tb_ctx.nb_tbs ? target_code_size /
                    tcg_ctx.tb_ctx.nb_tbs : 0,
            max_target_code_size);
1623
    cpu_fprintf(f, "TB avg host size    %td bytes (expansion ratio: %0.1f)\n",
1624 1625 1626 1627 1628 1629 1630 1631 1632
            tcg_ctx.tb_ctx.nb_tbs ? (tcg_ctx.code_gen_ptr -
                                     tcg_ctx.code_gen_buffer) /
                                     tcg_ctx.tb_ctx.nb_tbs : 0,
                target_code_size ? (double) (tcg_ctx.code_gen_ptr -
                                             tcg_ctx.code_gen_buffer) /
                                             target_code_size : 0);
    cpu_fprintf(f, "cross page TB count %d (%d%%)\n", cross_page,
            tcg_ctx.tb_ctx.nb_tbs ? (cross_page * 100) /
                                    tcg_ctx.tb_ctx.nb_tbs : 0);
1633 1634
    cpu_fprintf(f, "direct jump count   %d (%d%%) (2 jumps=%d %d%%)\n",
                direct_jmp_count,
1635 1636
                tcg_ctx.tb_ctx.nb_tbs ? (direct_jmp_count * 100) /
                        tcg_ctx.tb_ctx.nb_tbs : 0,
1637
                direct_jmp2_count,
1638 1639
                tcg_ctx.tb_ctx.nb_tbs ? (direct_jmp2_count * 100) /
                        tcg_ctx.tb_ctx.nb_tbs : 0);
1640
    cpu_fprintf(f, "\nStatistics:\n");
1641 1642 1643
    cpu_fprintf(f, "TB flush count      %d\n", tcg_ctx.tb_ctx.tb_flush_count);
    cpu_fprintf(f, "TB invalidate count %d\n",
            tcg_ctx.tb_ctx.tb_phys_invalidate_count);
1644 1645 1646 1647 1648 1649
    cpu_fprintf(f, "TLB flush count     %d\n", tlb_flush_count);
    tcg_dump_info(f, cpu_fprintf);
}

#else /* CONFIG_USER_ONLY */

1650
void cpu_interrupt(CPUState *cpu, int mask)
1651
{
1652
    cpu->interrupt_request |= mask;
1653
    cpu->tcg_exit_req = 1;
1654 1655 1656 1657 1658 1659 1660 1661 1662
}

/*
 * Walks guest process memory "regions" one by one
 * and calls callback function 'fn' for each region.
 */
struct walk_memory_regions_data {
    walk_memory_regions_fn fn;
    void *priv;
1663
    target_ulong start;
1664 1665 1666 1667
    int prot;
};

static int walk_memory_regions_end(struct walk_memory_regions_data *data,
1668
                                   target_ulong end, int new_prot)
1669
{
1670
    if (data->start != -1u) {
1671 1672 1673 1674 1675 1676
        int rc = data->fn(data->priv, data->start, end, data->prot);
        if (rc != 0) {
            return rc;
        }
    }

1677
    data->start = (new_prot ? end : -1u);
1678 1679 1680 1681 1682 1683
    data->prot = new_prot;

    return 0;
}

static int walk_memory_regions_1(struct walk_memory_regions_data *data,
1684
                                 target_ulong base, int level, void **lp)
1685
{
1686
    target_ulong pa;
1687 1688 1689 1690 1691 1692 1693 1694 1695
    int i, rc;

    if (*lp == NULL) {
        return walk_memory_regions_end(data, base, 0);
    }

    if (level == 0) {
        PageDesc *pd = *lp;

1696
        for (i = 0; i < V_L2_SIZE; ++i) {
1697 1698 1699 1700 1701 1702 1703 1704 1705 1706 1707 1708 1709
            int prot = pd[i].flags;

            pa = base | (i << TARGET_PAGE_BITS);
            if (prot != data->prot) {
                rc = walk_memory_regions_end(data, pa, prot);
                if (rc != 0) {
                    return rc;
                }
            }
        }
    } else {
        void **pp = *lp;

1710
        for (i = 0; i < V_L2_SIZE; ++i) {
1711
            pa = base | ((target_ulong)i <<
1712
                (TARGET_PAGE_BITS + V_L2_BITS * level));
1713 1714 1715 1716 1717 1718 1719 1720 1721 1722 1723 1724 1725 1726 1727 1728 1729
            rc = walk_memory_regions_1(data, pa, level - 1, pp + i);
            if (rc != 0) {
                return rc;
            }
        }
    }

    return 0;
}

int walk_memory_regions(void *priv, walk_memory_regions_fn fn)
{
    struct walk_memory_regions_data data;
    uintptr_t i;

    data.fn = fn;
    data.priv = priv;
1730
    data.start = -1u;
1731 1732 1733
    data.prot = 0;

    for (i = 0; i < V_L1_SIZE; i++) {
1734
        int rc = walk_memory_regions_1(&data, (target_ulong)i << (V_L1_SHIFT + TARGET_PAGE_BITS),
1735
                                       V_L1_SHIFT / V_L2_BITS - 1, l1_map + i);
1736 1737 1738 1739 1740 1741 1742 1743
        if (rc != 0) {
            return rc;
        }
    }

    return walk_memory_regions_end(&data, 0, 0);
}

1744 1745
static int dump_region(void *priv, target_ulong start,
    target_ulong end, unsigned long prot)
1746 1747 1748
{
    FILE *f = (FILE *)priv;

1749 1750
    (void) fprintf(f, TARGET_FMT_lx"-"TARGET_FMT_lx
        " "TARGET_FMT_lx" %c%c%c\n",
1751 1752 1753 1754 1755 1756 1757 1758 1759 1760 1761
        start, end, end - start,
        ((prot & PAGE_READ) ? 'r' : '-'),
        ((prot & PAGE_WRITE) ? 'w' : '-'),
        ((prot & PAGE_EXEC) ? 'x' : '-'));

    return 0;
}

/* dump memory mappings */
void page_dump(FILE *f)
{
1762