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/*
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 *  qemu user main
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 *
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 *  Copyright (c) 2003-2008 Fabrice Bellard
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 *
 *  This program is free software; you can redistribute it and/or modify
 *  it under the terms of the GNU General Public License as published by
 *  the Free Software Foundation; either version 2 of the License, or
 *  (at your option) any later version.
 *
 *  This program is distributed in the hope that it will be useful,
 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *  GNU General Public License for more details.
 *
 *  You should have received a copy of the GNU General Public License
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 *  along with this program; if not, see <http://www.gnu.org/licenses/>.
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 */
#include <stdlib.h>
#include <stdio.h>
#include <stdarg.h>
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#include <string.h>
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#include <errno.h>
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#include <unistd.h>
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#include <sys/mman.h>
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#include <sys/syscall.h>
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#include <sys/resource.h>
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#include "qemu.h"
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#include "qemu-common.h"
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#include "cpu.h"
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#include "tcg.h"
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#include "qemu/timer.h"
#include "qemu/envlist.h"
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#include "elf.h"
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char *exec_path;

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int singlestep;
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const char *filename;
const char *argv0;
int gdbstub_port;
envlist_t *envlist;
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static const char *cpu_model;
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unsigned long mmap_min_addr;
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#if defined(CONFIG_USE_GUEST_BASE)
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unsigned long guest_base;
int have_guest_base;
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#if (TARGET_LONG_BITS == 32) && (HOST_LONG_BITS == 64)
/*
 * When running 32-on-64 we should make sure we can fit all of the possible
 * guest address space into a contiguous chunk of virtual host memory.
 *
 * This way we will never overlap with our own libraries or binaries or stack
 * or anything else that QEMU maps.
 */
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# ifdef TARGET_MIPS
/* MIPS only supports 31 bits of virtual address space for user space */
unsigned long reserved_va = 0x77000000;
# else
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unsigned long reserved_va = 0xf7000000;
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# endif
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#else
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unsigned long reserved_va;
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#endif
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#endif
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static void usage(void);

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static const char *interp_prefix = CONFIG_QEMU_INTERP_PREFIX;
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const char *qemu_uname_release;
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/* XXX: on x86 MAP_GROWSDOWN only works if ESP <= address + 32, so
   we allocate a bigger stack. Need a better solution, for example
   by remapping the process stack directly at the right place */
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unsigned long guest_stack_size = 8 * 1024 * 1024UL;
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void gemu_log(const char *fmt, ...)
{
    va_list ap;

    va_start(ap, fmt);
    vfprintf(stderr, fmt, ap);
    va_end(ap);
}

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#if defined(TARGET_I386)
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int cpu_get_pic_interrupt(CPUX86State *env)
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{
    return -1;
}
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#endif
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/***********************************************************/
/* Helper routines for implementing atomic operations.  */

/* To implement exclusive operations we force all cpus to syncronise.
   We don't require a full sync, only that no cpus are executing guest code.
   The alternative is to map target atomic ops onto host equivalents,
   which requires quite a lot of per host/target work.  */
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static pthread_mutex_t cpu_list_mutex = PTHREAD_MUTEX_INITIALIZER;
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static pthread_mutex_t exclusive_lock = PTHREAD_MUTEX_INITIALIZER;
static pthread_cond_t exclusive_cond = PTHREAD_COND_INITIALIZER;
static pthread_cond_t exclusive_resume = PTHREAD_COND_INITIALIZER;
static int pending_cpus;

/* Make sure everything is in a consistent state for calling fork().  */
void fork_start(void)
{
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    pthread_mutex_lock(&tcg_ctx.tb_ctx.tb_lock);
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    pthread_mutex_lock(&exclusive_lock);
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    mmap_fork_start();
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}

void fork_end(int child)
{
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    mmap_fork_end(child);
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    if (child) {
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        CPUState *cpu, *next_cpu;
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        /* Child processes created by fork() only have a single thread.
           Discard information about the parent threads.  */
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        CPU_FOREACH_SAFE(cpu, next_cpu) {
            if (cpu != thread_cpu) {
                QTAILQ_REMOVE(&cpus, thread_cpu, node);
            }
        }
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        pending_cpus = 0;
        pthread_mutex_init(&exclusive_lock, NULL);
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        pthread_mutex_init(&cpu_list_mutex, NULL);
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        pthread_cond_init(&exclusive_cond, NULL);
        pthread_cond_init(&exclusive_resume, NULL);
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        pthread_mutex_init(&tcg_ctx.tb_ctx.tb_lock, NULL);
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        gdbserver_fork((CPUArchState *)thread_cpu->env_ptr);
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    } else {
        pthread_mutex_unlock(&exclusive_lock);
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        pthread_mutex_unlock(&tcg_ctx.tb_ctx.tb_lock);
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    }
}

/* Wait for pending exclusive operations to complete.  The exclusive lock
   must be held.  */
static inline void exclusive_idle(void)
{
    while (pending_cpus) {
        pthread_cond_wait(&exclusive_resume, &exclusive_lock);
    }
}

/* Start an exclusive operation.
   Must only be called from outside cpu_arm_exec.   */
static inline void start_exclusive(void)
{
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    CPUState *other_cpu;

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    pthread_mutex_lock(&exclusive_lock);
    exclusive_idle();

    pending_cpus = 1;
    /* Make all other cpus stop executing.  */
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    CPU_FOREACH(other_cpu) {
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        if (other_cpu->running) {
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            pending_cpus++;
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            cpu_exit(other_cpu);
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        }
    }
    if (pending_cpus > 1) {
        pthread_cond_wait(&exclusive_cond, &exclusive_lock);
    }
}

/* Finish an exclusive operation.  */
static inline void end_exclusive(void)
{
    pending_cpus = 0;
    pthread_cond_broadcast(&exclusive_resume);
    pthread_mutex_unlock(&exclusive_lock);
}

/* Wait for exclusive ops to finish, and begin cpu execution.  */
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static inline void cpu_exec_start(CPUState *cpu)
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{
    pthread_mutex_lock(&exclusive_lock);
    exclusive_idle();
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    cpu->running = true;
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    pthread_mutex_unlock(&exclusive_lock);
}

/* Mark cpu as not executing, and release pending exclusive ops.  */
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static inline void cpu_exec_end(CPUState *cpu)
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{
    pthread_mutex_lock(&exclusive_lock);
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    cpu->running = false;
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    if (pending_cpus > 1) {
        pending_cpus--;
        if (pending_cpus == 1) {
            pthread_cond_signal(&exclusive_cond);
        }
    }
    exclusive_idle();
    pthread_mutex_unlock(&exclusive_lock);
}
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void cpu_list_lock(void)
{
    pthread_mutex_lock(&cpu_list_mutex);
}

void cpu_list_unlock(void)
{
    pthread_mutex_unlock(&cpu_list_mutex);
}
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#ifdef TARGET_I386
/***********************************************************/
/* CPUX86 core interface */

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void cpu_smm_update(CPUX86State *env)
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{
}

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uint64_t cpu_get_tsc(CPUX86State *env)
{
    return cpu_get_real_ticks();
}

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static void write_dt(void *ptr, unsigned long addr, unsigned long limit,
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                     int flags)
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{
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    unsigned int e1, e2;
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    uint32_t *p;
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    e1 = (addr << 16) | (limit & 0xffff);
    e2 = ((addr >> 16) & 0xff) | (addr & 0xff000000) | (limit & 0x000f0000);
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    e2 |= flags;
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    p = ptr;
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    p[0] = tswap32(e1);
    p[1] = tswap32(e2);
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}

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static uint64_t *idt_table;
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#ifdef TARGET_X86_64
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static void set_gate64(void *ptr, unsigned int type, unsigned int dpl,
                       uint64_t addr, unsigned int sel)
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{
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    uint32_t *p, e1, e2;
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    e1 = (addr & 0xffff) | (sel << 16);
    e2 = (addr & 0xffff0000) | 0x8000 | (dpl << 13) | (type << 8);
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    p = ptr;
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    p[0] = tswap32(e1);
    p[1] = tswap32(e2);
    p[2] = tswap32(addr >> 32);
    p[3] = 0;
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}
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/* only dpl matters as we do only user space emulation */
static void set_idt(int n, unsigned int dpl)
{
    set_gate64(idt_table + n * 2, 0, dpl, 0, 0);
}
#else
static void set_gate(void *ptr, unsigned int type, unsigned int dpl,
                     uint32_t addr, unsigned int sel)
{
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    uint32_t *p, e1, e2;
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    e1 = (addr & 0xffff) | (sel << 16);
    e2 = (addr & 0xffff0000) | 0x8000 | (dpl << 13) | (type << 8);
    p = ptr;
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    p[0] = tswap32(e1);
    p[1] = tswap32(e2);
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}

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/* only dpl matters as we do only user space emulation */
static void set_idt(int n, unsigned int dpl)
{
    set_gate(idt_table + n, 0, dpl, 0, 0);
}
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#endif
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void cpu_loop(CPUX86State *env)
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{
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    CPUState *cs = CPU(x86_env_get_cpu(env));
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    int trapnr;
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    abi_ulong pc;
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    target_siginfo_t info;
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    for(;;) {
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        trapnr = cpu_x86_exec(env);
        switch(trapnr) {
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        case 0x80:
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            /* linux syscall from int $0x80 */
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            env->regs[R_EAX] = do_syscall(env,
                                          env->regs[R_EAX],
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                                          env->regs[R_EBX],
                                          env->regs[R_ECX],
                                          env->regs[R_EDX],
                                          env->regs[R_ESI],
                                          env->regs[R_EDI],
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                                          env->regs[R_EBP],
                                          0, 0);
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            break;
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#ifndef TARGET_ABI32
        case EXCP_SYSCALL:
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            /* linux syscall from syscall instruction */
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            env->regs[R_EAX] = do_syscall(env,
                                          env->regs[R_EAX],
                                          env->regs[R_EDI],
                                          env->regs[R_ESI],
                                          env->regs[R_EDX],
                                          env->regs[10],
                                          env->regs[8],
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                                          env->regs[9],
                                          0, 0);
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            break;
#endif
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        case EXCP0B_NOSEG:
        case EXCP0C_STACK:
            info.si_signo = SIGBUS;
            info.si_errno = 0;
            info.si_code = TARGET_SI_KERNEL;
            info._sifields._sigfault._addr = 0;
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            queue_signal(env, info.si_signo, &info);
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            break;
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        case EXCP0D_GPF:
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            /* XXX: potential problem if ABI32 */
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#ifndef TARGET_X86_64
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            if (env->eflags & VM_MASK) {
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                handle_vm86_fault(env);
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            } else
#endif
            {
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                info.si_signo = SIGSEGV;
                info.si_errno = 0;
                info.si_code = TARGET_SI_KERNEL;
                info._sifields._sigfault._addr = 0;
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                queue_signal(env, info.si_signo, &info);
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            }
            break;
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        case EXCP0E_PAGE:
            info.si_signo = SIGSEGV;
            info.si_errno = 0;
            if (!(env->error_code & 1))
                info.si_code = TARGET_SEGV_MAPERR;
            else
                info.si_code = TARGET_SEGV_ACCERR;
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            info._sifields._sigfault._addr = env->cr[2];
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            queue_signal(env, info.si_signo, &info);
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            break;
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        case EXCP00_DIVZ:
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#ifndef TARGET_X86_64
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            if (env->eflags & VM_MASK) {
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                handle_vm86_trap(env, trapnr);
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            } else
#endif
            {
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                /* division by zero */
                info.si_signo = SIGFPE;
                info.si_errno = 0;
                info.si_code = TARGET_FPE_INTDIV;
                info._sifields._sigfault._addr = env->eip;
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                queue_signal(env, info.si_signo, &info);
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            }
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            break;
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        case EXCP01_DB:
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        case EXCP03_INT3:
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#ifndef TARGET_X86_64
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            if (env->eflags & VM_MASK) {
                handle_vm86_trap(env, trapnr);
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            } else
#endif
            {
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                info.si_signo = SIGTRAP;
                info.si_errno = 0;
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                if (trapnr == EXCP01_DB) {
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                    info.si_code = TARGET_TRAP_BRKPT;
                    info._sifields._sigfault._addr = env->eip;
                } else {
                    info.si_code = TARGET_SI_KERNEL;
                    info._sifields._sigfault._addr = 0;
                }
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                queue_signal(env, info.si_signo, &info);
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            }
            break;
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        case EXCP04_INTO:
        case EXCP05_BOUND:
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#ifndef TARGET_X86_64
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            if (env->eflags & VM_MASK) {
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                handle_vm86_trap(env, trapnr);
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            } else
#endif
            {
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                info.si_signo = SIGSEGV;
                info.si_errno = 0;
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                info.si_code = TARGET_SI_KERNEL;
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                info._sifields._sigfault._addr = 0;
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                queue_signal(env, info.si_signo, &info);
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            }
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            break;
        case EXCP06_ILLOP:
            info.si_signo = SIGILL;
            info.si_errno = 0;
            info.si_code = TARGET_ILL_ILLOPN;
            info._sifields._sigfault._addr = env->eip;
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            queue_signal(env, info.si_signo, &info);
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            break;
        case EXCP_INTERRUPT:
            /* just indicate that signals should be handled asap */
            break;
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        case EXCP_DEBUG:
            {
                int sig;

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                sig = gdb_handlesig(cs, TARGET_SIGTRAP);
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                if (sig)
                  {
                    info.si_signo = sig;
                    info.si_errno = 0;
                    info.si_code = TARGET_TRAP_BRKPT;
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                    queue_signal(env, info.si_signo, &info);
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                  }
            }
            break;
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        default:
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            pc = env->segs[R_CS].base + env->eip;
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            fprintf(stderr, "qemu: 0x%08lx: unhandled CPU exception 0x%x - aborting\n",
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                    (long)pc, trapnr);
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            abort();
        }
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        process_pending_signals(env);
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    }
}
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#endif

#ifdef TARGET_ARM

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#define get_user_code_u32(x, gaddr, doswap)             \
    ({ abi_long __r = get_user_u32((x), (gaddr));       \
        if (!__r && (doswap)) {                         \
            (x) = bswap32(x);                           \
        }                                               \
        __r;                                            \
    })

#define get_user_code_u16(x, gaddr, doswap)             \
    ({ abi_long __r = get_user_u16((x), (gaddr));       \
        if (!__r && (doswap)) {                         \
            (x) = bswap16(x);                           \
        }                                               \
        __r;                                            \
    })

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#ifdef TARGET_ABI32
/* Commpage handling -- there is no commpage for AArch64 */

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/*
 * See the Linux kernel's Documentation/arm/kernel_user_helpers.txt
 * Input:
 * r0 = pointer to oldval
 * r1 = pointer to newval
 * r2 = pointer to target value
 *
 * Output:
 * r0 = 0 if *ptr was changed, non-0 if no exchange happened
 * C set if *ptr was changed, clear if no exchange happened
 *
 * Note segv's in kernel helpers are a bit tricky, we can set the
 * data address sensibly but the PC address is just the entry point.
 */
static void arm_kernel_cmpxchg64_helper(CPUARMState *env)
{
    uint64_t oldval, newval, val;
    uint32_t addr, cpsr;
    target_siginfo_t info;

    /* Based on the 32 bit code in do_kernel_trap */

    /* XXX: This only works between threads, not between processes.
       It's probably possible to implement this with native host
       operations. However things like ldrex/strex are much harder so
       there's not much point trying.  */
    start_exclusive();
    cpsr = cpsr_read(env);
    addr = env->regs[2];

    if (get_user_u64(oldval, env->regs[0])) {
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        env->exception.vaddress = env->regs[0];
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        goto segv;
    };

    if (get_user_u64(newval, env->regs[1])) {
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        env->exception.vaddress = env->regs[1];
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        goto segv;
    };

    if (get_user_u64(val, addr)) {
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        env->exception.vaddress = addr;
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        goto segv;
    }

    if (val == oldval) {
        val = newval;

        if (put_user_u64(val, addr)) {
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            env->exception.vaddress = addr;
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            goto segv;
        };

        env->regs[0] = 0;
        cpsr |= CPSR_C;
    } else {
        env->regs[0] = -1;
        cpsr &= ~CPSR_C;
    }
    cpsr_write(env, cpsr, CPSR_C);
    end_exclusive();
    return;

segv:
    end_exclusive();
    /* We get the PC of the entry address - which is as good as anything,
       on a real kernel what you get depends on which mode it uses. */
    info.si_signo = SIGSEGV;
    info.si_errno = 0;
    /* XXX: check env->error_code */
    info.si_code = TARGET_SEGV_MAPERR;
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    info._sifields._sigfault._addr = env->exception.vaddress;
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    queue_signal(env, info.si_signo, &info);

    end_exclusive();
}

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/* Handle a jump to the kernel code page.  */
static int
do_kernel_trap(CPUARMState *env)
{
    uint32_t addr;
    uint32_t cpsr;
    uint32_t val;

    switch (env->regs[15]) {
    case 0xffff0fa0: /* __kernel_memory_barrier */
        /* ??? No-op. Will need to do better for SMP.  */
        break;
    case 0xffff0fc0: /* __kernel_cmpxchg */
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         /* XXX: This only works between threads, not between processes.
            It's probably possible to implement this with native host
            operations. However things like ldrex/strex are much harder so
            there's not much point trying.  */
        start_exclusive();
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        cpsr = cpsr_read(env);
        addr = env->regs[2];
        /* FIXME: This should SEGV if the access fails.  */
        if (get_user_u32(val, addr))
            val = ~env->regs[0];
        if (val == env->regs[0]) {
            val = env->regs[1];
            /* FIXME: Check for segfaults.  */
            put_user_u32(val, addr);
            env->regs[0] = 0;
            cpsr |= CPSR_C;
        } else {
            env->regs[0] = -1;
            cpsr &= ~CPSR_C;
        }
        cpsr_write(env, cpsr, CPSR_C);
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        end_exclusive();
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        break;
    case 0xffff0fe0: /* __kernel_get_tls */
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        env->regs[0] = env->cp15.tpidrro_el0;
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        break;
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    case 0xffff0f60: /* __kernel_cmpxchg64 */
        arm_kernel_cmpxchg64_helper(env);
        break;

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    default:
        return 1;
    }
    /* Jump back to the caller.  */
    addr = env->regs[14];
    if (addr & 1) {
        env->thumb = 1;
        addr &= ~1;
    }
    env->regs[15] = addr;

    return 0;
}

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/* Store exclusive handling for AArch32 */
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static int do_strex(CPUARMState *env)
{
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    uint64_t val;
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    int size;
    int rc = 1;
    int segv = 0;
    uint32_t addr;
    start_exclusive();
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    if (env->exclusive_addr != env->exclusive_test) {
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        goto fail;
    }
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    /* We know we're always AArch32 so the address is in uint32_t range
     * unless it was the -1 exclusive-monitor-lost value (which won't
     * match exclusive_test above).
     */
    assert(extract64(env->exclusive_addr, 32, 32) == 0);
    addr = env->exclusive_addr;
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    size = env->exclusive_info & 0xf;
    switch (size) {
    case 0:
        segv = get_user_u8(val, addr);
        break;
    case 1:
        segv = get_user_u16(val, addr);
        break;
    case 2:
    case 3:
        segv = get_user_u32(val, addr);
        break;
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    default:
        abort();
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    }
    if (segv) {
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        env->exception.vaddress = addr;
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        goto done;
    }
    if (size == 3) {
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        uint32_t valhi;
        segv = get_user_u32(valhi, addr + 4);
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        if (segv) {
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            env->exception.vaddress = addr + 4;
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            goto done;
        }
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        val = deposit64(val, 32, 32, valhi);
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    }
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    if (val != env->exclusive_val) {
        goto fail;
    }

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    val = env->regs[(env->exclusive_info >> 8) & 0xf];
    switch (size) {
    case 0:
        segv = put_user_u8(val, addr);
        break;
    case 1:
        segv = put_user_u16(val, addr);
        break;
    case 2:
    case 3:
        segv = put_user_u32(val, addr);
        break;
    }
    if (segv) {
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        env->exception.vaddress = addr;
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        goto done;
    }
    if (size == 3) {
        val = env->regs[(env->exclusive_info >> 12) & 0xf];
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        segv = put_user_u32(val, addr + 4);
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        if (segv) {
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            env->exception.vaddress = addr + 4;
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            goto done;
        }
    }
    rc = 0;
fail:
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    env->regs[15] += 4;
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    env->regs[(env->exclusive_info >> 4) & 0xf] = rc;
done:
    end_exclusive();
    return segv;
}

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void cpu_loop(CPUARMState *env)
{
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    CPUState *cs = CPU(arm_env_get_cpu(env));
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    int trapnr;
    unsigned int n, insn;
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    target_siginfo_t info;
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    uint32_t addr;
678

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    for(;;) {
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        cpu_exec_start(cs);
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        trapnr = cpu_arm_exec(env);
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        cpu_exec_end(cs);
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        switch(trapnr) {
        case EXCP_UDEF:
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            {
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                TaskState *ts = cs->opaque;
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                uint32_t opcode;
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                int rc;
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                /* we handle the FPU emulation here, as Linux */
                /* we get the opcode */
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                /* FIXME - what to do if get_user() fails? */
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                get_user_code_u32(opcode, env->regs[15], env->bswap_code);
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                rc = EmulateAll(opcode, &ts->fpa, env);
                if (rc == 0) { /* illegal instruction */
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                    info.si_signo = SIGILL;
                    info.si_errno = 0;
                    info.si_code = TARGET_ILL_ILLOPN;
                    info._sifields._sigfault._addr = env->regs[15];
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                    queue_signal(env, info.si_signo, &info);
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                } else if (rc < 0) { /* FP exception */
                    int arm_fpe=0;

                    /* translate softfloat flags to FPSR flags */
                    if (-rc & float_flag_invalid)
                      arm_fpe |= BIT_IOC;
                    if (-rc & float_flag_divbyzero)
                      arm_fpe |= BIT_DZC;
                    if (-rc & float_flag_overflow)
                      arm_fpe |= BIT_OFC;
                    if (-rc & float_flag_underflow)
                      arm_fpe |= BIT_UFC;
                    if (-rc & float_flag_inexact)
                      arm_fpe |= BIT_IXC;

                    FPSR fpsr = ts->fpa.fpsr;
                    //printf("fpsr 0x%x, arm_fpe 0x%x\n",fpsr,arm_fpe);

                    if (fpsr & (arm_fpe << 16)) { /* exception enabled? */
                      info.si_signo = SIGFPE;
                      info.si_errno = 0;

                      /* ordered by priority, least first */
                      if (arm_fpe & BIT_IXC) info.si_code = TARGET_FPE_FLTRES;
                      if (arm_fpe & BIT_UFC) info.si_code = TARGET_FPE_FLTUND;
                      if (arm_fpe & BIT_OFC) info.si_code = TARGET_FPE_FLTOVF;
                      if (arm_fpe & BIT_DZC) info.si_code = TARGET_FPE_FLTDIV;
                      if (arm_fpe & BIT_IOC) info.si_code = TARGET_FPE_FLTINV;

                      info._sifields._sigfault._addr = env->regs[15];
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                      queue_signal(env, info.si_signo, &info);
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                    } else {
                      env->regs[15] += 4;
                    }

                    /* accumulate unenabled exceptions */
                    if ((!(fpsr & BIT_IXE)) && (arm_fpe & BIT_IXC))
                      fpsr |= BIT_IXC;
                    if ((!(fpsr & BIT_UFE)) && (arm_fpe & BIT_UFC))
                      fpsr |= BIT_UFC;
                    if ((!(fpsr & BIT_OFE)) && (arm_fpe & BIT_OFC))
                      fpsr |= BIT_OFC;
                    if ((!(fpsr & BIT_DZE)) && (arm_fpe & BIT_DZC))
                      fpsr |= BIT_DZC;
                    if ((!(fpsr & BIT_IOE)) && (arm_fpe & BIT_IOC))
                      fpsr |= BIT_IOC;
                    ts->fpa.fpsr=fpsr;
                } else { /* everything OK */
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                    /* increment PC */
                    env->regs[15] += 4;
                }
            }
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            break;
        case EXCP_SWI:
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        case EXCP_BKPT:
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            {
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                env->eabi = 1;
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                /* system call */
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                if (trapnr == EXCP_BKPT) {
                    if (env->thumb) {
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                        /* FIXME - what to do if get_user() fails? */
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                        get_user_code_u16(insn, env->regs[15], env->bswap_code);
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                        n = insn & 0xff;
                        env->regs[15] += 2;
                    } else {
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                        /* FIXME - what to do if get_user() fails? */
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                        get_user_code_u32(insn, env->regs[15], env->bswap_code);
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                        n = (insn & 0xf) | ((insn >> 4) & 0xff0);
                        env->regs[15] += 4;
                    }
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                } else {
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                    if (env->thumb) {
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                        /* FIXME - what to do if get_user() fails? */
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                        get_user_code_u16(insn, env->regs[15] - 2,
                                          env->bswap_code);
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                        n = insn & 0xff;
                    } else {
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                        /* FIXME - what to do if get_user() fails? */
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                        get_user_code_u32(insn, env->regs[15] - 4,
                                          env->bswap_code);
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                        n = insn & 0xffffff;
                    }
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                }

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                if (n == ARM_NR_cacheflush) {
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                    /* nop */
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                } else if (n == ARM_NR_semihosting
                           || n == ARM_NR_thumb_semihosting) {
                    env->regs[0] = do_arm_semihosting (env);
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                } else if (n == 0 || n >= ARM_SYSCALL_BASE || env->thumb) {
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                    /* linux syscall */
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                    if (env->thumb || n == 0) {
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                        n = env->regs[7];
                    } else {
                        n -= ARM_SYSCALL_BASE;
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                        env->eabi = 0;
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                    }
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                    if ( n > ARM_NR_BASE) {
                        switch (n) {
                        case ARM_NR_cacheflush:
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                            /* nop */
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                            break;
                        case ARM_NR_set_tls:
                            cpu_set_tls(env, env->regs[0]);
                            env->regs[0] = 0;
                            break;
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                        case ARM_NR_breakpoint:
                            env->regs[15] -= env->thumb ? 2 : 4;
                            goto excp_debug;
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                        default:
                            gemu_log("qemu: Unsupported ARM syscall: 0x%x\n",
                                     n);
                            env->regs[0] = -TARGET_ENOSYS;
                            break;
                        }
                    } else {
                        env->regs[0] = do_syscall(env,
                                                  n,
                                                  env->regs[0],
                                                  env->regs[1],
                                                  env->regs[2],
                                                  env->regs[3],
                                                  env->regs[4],
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                                                  env->regs[5],
                                                  0, 0);
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                    }
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                } else {
                    goto error;
                }
            }
            break;
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        case EXCP_INTERRUPT:
            /* just indicate that signals should be handled asap */
            break;
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        case EXCP_STREX:
            if (!do_strex(env)) {
                break;
            }
            /* fall through for segv */
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        case EXCP_PREFETCH_ABORT:
        case EXCP_DATA_ABORT:
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            addr = env->exception.vaddress;
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            {
                info.si_signo = SIGSEGV;
                info.si_errno = 0;
                /* XXX: check env->error_code */
                info.si_code = TARGET_SEGV_MAPERR;
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                info._sifields._sigfault._addr = addr;
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                queue_signal(env, info.si_signo, &info);
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            }
            break;
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        case EXCP_DEBUG:
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        excp_debug:
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            {
                int sig;

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                sig = gdb_handlesig(cs, TARGET_SIGTRAP);
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                if (sig)
                  {
                    info.si_signo = sig;
                    info.si_errno = 0;
                    info.si_code = TARGET_TRAP_BRKPT;
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                    queue_signal(env, info.si_signo, &info);
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                  }
            }
            break;
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        case EXCP_KERNEL_TRAP:
            if (do_kernel_trap(env))
              goto error;
            break;
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        default:
        error:
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            fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n",
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                    trapnr);
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            cpu_dump_state(cs, stderr, fprintf, 0);
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            abort();
        }
        process_pending_signals(env);
    }
}

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#else

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/*
 * Handle AArch64 store-release exclusive
 *
 * rs = gets the status result of store exclusive
 * rt = is the register that is stored
 * rt2 = is the second register store (in STP)
 *
 */
static int do_strex_a64(CPUARMState *env)
{
    uint64_t val;
    int size;
    bool is_pair;
    int rc = 1;
    int segv = 0;
    uint64_t addr;
    int rs, rt, rt2;

    start_exclusive();
    /* size | is_pair << 2 | (rs << 4) | (rt << 9) | (rt2 << 14)); */
    size = extract32(env->exclusive_info, 0, 2);
    is_pair = extract32(env->exclusive_info, 2, 1);
    rs = extract32(env->exclusive_info, 4, 5);
    rt = extract32(env->exclusive_info, 9, 5);
    rt2 = extract32(env->exclusive_info, 14, 5);

    addr = env->exclusive_addr;

    if (addr != env->exclusive_test) {
        goto finish;
    }

    switch (size) {
    case 0:
        segv = get_user_u8(val, addr);
        break;
    case 1:
        segv = get_user_u16(val, addr);
        break;
    case 2:
        segv = get_user_u32(val, addr);
        break;
    case 3:
        segv = get_user_u64(val, addr);
        break;
    default:
        abort();
    }
    if (segv) {
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        env->exception.vaddress = addr;
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        goto error;
    }
    if (val != env->exclusive_val) {
        goto finish;
    }
    if (is_pair) {
        if (size == 2) {
            segv = get_user_u32(val, addr + 4);
        } else {
            segv = get_user_u64(val, addr + 8);
        }
        if (segv) {
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            env->exception.vaddress = addr + (size == 2 ? 4 : 8);
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            goto error;
        }
        if (val != env->exclusive_high) {
            goto finish;
        }
    }
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    /* handle the zero register */
    val = rt == 31 ? 0 : env->xregs[rt];
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    switch (size) {
    case 0:
        segv = put_user_u8(val, addr);
        break;
    case 1:
        segv = put_user_u16(val, addr);
        break;
    case 2:
        segv = put_user_u32(val, addr);
        break;
    case 3:
        segv = put_user_u64(val, addr);
        break;
    }
    if (segv) {
        goto error;
    }
    if (is_pair) {
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        /* handle the zero register */
        val = rt2 == 31 ? 0 : env->xregs[rt2];
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        if (size == 2) {
            segv = put_user_u32(val, addr + 4);
        } else {
            segv = put_user_u64(val, addr + 8);
        }
        if (segv) {
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            env->exception.vaddress = addr + (size == 2 ? 4 : 8);
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            goto error;
        }
    }
    rc = 0;
finish:
    env->pc += 4;
    /* rs == 31 encodes a write to the ZR, thus throwing away
     * the status return. This is rather silly but valid.
     */
    if (rs < 31) {
        env->xregs[rs] = rc;
    }
error:
    /* instruction faulted, PC does not advance */
    /* either way a strex releases any exclusive lock we have */
    env->exclusive_addr = -1;
    end_exclusive();
    return segv;
}

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/* AArch64 main loop */
void cpu_loop(CPUARMState *env)
{
    CPUState *cs = CPU(arm_env_get_cpu(env));
    int trapnr, sig;
    target_siginfo_t info;

    for (;;) {
        cpu_exec_start(cs);
        trapnr = cpu_arm_exec(env);
        cpu_exec_end(cs);

        switch (trapnr) {
        case EXCP_SWI:
            env->xregs[0] = do_syscall(env,
                                       env->xregs[8],
                                       env->xregs[0],
                                       env->xregs[1],
                                       env->xregs[2],
                                       env->xregs[3],
                                       env->xregs[4],
                                       env->xregs[5],
                                       0, 0);
            break;
        case EXCP_INTERRUPT:
            /* just indicate that signals should be handled asap */
            break;
        case EXCP_UDEF:
            info.si_signo = SIGILL;
            info.si_errno = 0;
            info.si_code = TARGET_ILL_ILLOPN;
            info._sifields._sigfault._addr = env->pc;
            queue_signal(env, info.si_signo, &info);
            break;
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        case EXCP_STREX:
            if (!do_strex_a64(env)) {
                break;
            }
            /* fall through for segv */
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        case EXCP_PREFETCH_ABORT:
        case EXCP_DATA_ABORT:
            info.si_signo = SIGSEGV;
            info.si_errno = 0;
            /* XXX: check env->error_code */
            info.si_code = TARGET_SEGV_MAPERR;
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            info._sifields._sigfault._addr = env->exception.vaddress;
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            queue_signal(env, info.si_signo, &info);
            break;
        case EXCP_DEBUG:
        case EXCP_BKPT:
            sig = gdb_handlesig(cs, TARGET_SIGTRAP);
            if (sig) {
                info.si_signo = sig;
                info.si_errno = 0;
                info.si_code = TARGET_TRAP_BRKPT;
                queue_signal(env, info.si_signo, &info);
            }
            break;
        default:
            fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n",
                    trapnr);
            cpu_dump_state(cs, stderr, fprintf, 0);
            abort();
        }
        process_pending_signals(env);
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        /* Exception return on AArch64 always clears the exclusive monitor,
         * so any return to running guest code implies this.
         * A strex (successful or otherwise) also clears the monitor, so
         * we don't need to specialcase EXCP_STREX.
         */
        env->exclusive_addr = -1;
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    }
}
#endif /* ndef TARGET_ABI32 */

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#endif
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#ifdef TARGET_UNICORE32

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void cpu_loop(CPUUniCore32State *env)
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{
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    CPUState *cs = CPU(uc32_env_get_cpu(env));
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    int trapnr;
    unsigned int n, insn;
    target_siginfo_t info;

    for (;;) {
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        cpu_exec_start(cs);
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        trapnr = uc32_cpu_exec(env);
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        cpu_exec_end(cs);
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        switch (trapnr) {
        case UC32_EXCP_PRIV:
            {
                /* system call */
                get_user_u32(insn, env->regs[31] - 4);
                n = insn & 0xffffff;

                if (n >= UC32_SYSCALL_BASE) {
                    /* linux syscall */
                    n -= UC32_SYSCALL_BASE;
                    if (n == UC32_SYSCALL_NR_set_tls) {
                            cpu_set_tls(env, env->regs[0]);
                            env->regs[0] = 0;
                    } else {
                        env->regs[0] = do_syscall(env,
                                                  n,
                                                  env->regs[0],
                                                  env->regs[1],
                                                  env->regs[2],
                                                  env->regs[3],
                                                  env->regs[4],
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                                                  env->regs[5],
                                                  0, 0);
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                    }
                } else {
                    goto error;
                }
            }
            break;
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        case UC32_EXCP_DTRAP:
        case UC32_EXCP_ITRAP:
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            info.si_signo = SIGSEGV;
            info.si_errno = 0;
            /* XXX: check env->error_code */
            info.si_code = TARGET_SEGV_MAPERR;
            info._sifields._sigfault._addr = env->cp0.c4_faultaddr;
            queue_signal(env, info.si_signo, &info);
            break;
        case EXCP_INTERRUPT:
            /* just indicate that signals should be handled asap */
            break;
        case EXCP_DEBUG:
            {
                int sig;

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                sig = gdb_handlesig(cs, TARGET_SIGTRAP);
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                if (sig) {
                    info.si_signo = sig;
                    info.si_errno = 0;
                    info.si_code = TARGET_TRAP_BRKPT;
                    queue_signal(env, info.si_signo, &info);
                }
            }
            break;
        default:
            goto error;
        }
        process_pending_signals(env);
    }

error:
    fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr);
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    cpu_dump_state(cs, stderr, fprintf, 0);
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    abort();
}
#endif

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#ifdef TARGET_SPARC
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#define SPARC64_STACK_BIAS 2047
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//#define DEBUG_WIN

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/* WARNING: dealing with register windows _is_ complicated. More info
   can be found at http://www.sics.se/~psm/sparcstack.html */
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static inline int get_reg_index(CPUSPARCState *env, int cwp, int index)
{
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    index = (index + cwp * 16) % (16 * env->nwindows);
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    /* wrap handling : if cwp is on the last window, then we use the
       registers 'after' the end */
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    if (index < 8 && env->cwp == env->nwindows - 1)
        index += 16 * env->nwindows;
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    return index;
}

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/* save the register window 'cwp1' */
static inline void save_window_offset(CPUSPARCState *env, int cwp1)
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{
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    unsigned int i;
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    abi_ulong sp_ptr;
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    sp_ptr = env->regbase[get_reg_index(env, cwp1, 6)];
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#ifdef TARGET_SPARC64
    if (sp_ptr & 3)
        sp_ptr += SPARC64_STACK_BIAS;
#endif
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#if defined(DEBUG_WIN)
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    printf("win_overflow: sp_ptr=0x" TARGET_ABI_FMT_lx " save_cwp=%d\n",
           sp_ptr, cwp1);
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#endif
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    for(i = 0; i < 16; i++) {
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        /* FIXME - what to do if put_user() fails? */
        put_user_ual(env->regbase[get_reg_index(env, cwp1, 8 + i)], sp_ptr);
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        sp_ptr += sizeof(abi_ulong);
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    }
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}

static void save_window(CPUSPARCState *env)
{
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#ifndef TARGET_SPARC64
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    unsigned int new_wim;
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    new_wim = ((env->wim >> 1) | (env->wim << (env->nwindows - 1))) &
        ((1LL << env->nwindows) - 1);
    save_window_offset(env, cpu_cwp_dec(env, env->cwp - 2));
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    env->wim = new_wim;
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#else
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    save_window_offset(env, cpu_cwp_dec(env, env->cwp - 2));
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    env->cansave++;
    env->canrestore--;
#endif
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}

static void restore_window(CPUSPARCState *env)
{
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#ifndef TARGET_SPARC64
    unsigned int new_wim;
#endif
    unsigned int i, cwp1;
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    abi_ulong sp_ptr;
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#ifndef TARGET_SPARC64
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    new_wim = ((env->wim << 1) | (env->wim >> (env->nwindows - 1))) &
        ((1LL << env->nwindows) - 1);
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#endif
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    /* restore the invalid window */
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    cwp1 = cpu_cwp_inc(env, env->cwp + 1);
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    sp_ptr = env->regbase[get_reg_index(env, cwp1, 6)];
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#ifdef TARGET_SPARC64
    if (sp_ptr & 3)
        sp_ptr += SPARC64_STACK_BIAS;
#endif
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#if defined(DEBUG_WIN)
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    printf("win_underflow: sp_ptr=0x" TARGET_ABI_FMT_lx " load_cwp=%d\n",
           sp_ptr, cwp1);
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#endif
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    for(i = 0; i < 16; i++) {
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        /* FIXME - what to do if get_user() fails? */
        get_user_ual(env->regbase[get_reg_index(env, cwp1, 8 + i)], sp_ptr);
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        sp_ptr += sizeof(abi_ulong);
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    }
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#ifdef TARGET_SPARC64
    env->canrestore++;
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    if (env->cleanwin < env->nwindows - 1)
        env->cleanwin++;
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    env->cansave--;
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#else
    env->wim = new_wim;
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#endif
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}

static void flush_windows(CPUSPARCState *env)
{
    int offset, cwp1;
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    offset = 1;
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    for(;;) {
        /* if restore would invoke restore_window(), then we can stop */
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        cwp1 = cpu_cwp_inc(env, env->cwp + offset);
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#ifndef TARGET_SPARC64
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        if (env->wim & (1 << cwp1))
            break;
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#else
        if (env->canrestore == 0)
            break;
        env->cansave++;
        env->canrestore--;
#endif
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        save_window_offset(env, cwp1);
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        offset++;
    }
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    cwp1 = cpu_cwp_inc(env, env->cwp + 1);
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#ifndef TARGET_SPARC64
    /* set wim so that restore will reload the registers */
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    env->wim = 1 << cwp1;
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#endif
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#if defined(DEBUG_WIN)
    printf("flush_windows: nb=%d\n", offset - 1);
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#endif
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}
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void cpu_loop (CPUSPARCState *env)
{
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    CPUState *cs = CPU(sparc_env_get_cpu(env));
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    int trapnr;
    abi_long ret;
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    target_siginfo_t info;
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    while (1) {
        trapnr = cpu_sparc_exec (env);
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        /* Compute PSR before exposing state.  */
        if (env->cc_op != CC_OP_FLAGS) {
            cpu_get_psr(env);
        }

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        switch (trapnr) {
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#ifndef TARGET_SPARC64
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        case 0x88:
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        case 0x90:
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#else
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        case 0x110:
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        case 0x16d:
#endif
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            ret = do_syscall (env, env->gregs[1],
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                              env->regwptr[0], env->regwptr[1],
                              env->regwptr[2], env->regwptr[3],
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                              env->regwptr[4], env->regwptr[5],
                              0, 0);
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            if ((abi_ulong)ret >= (abi_ulong)(-515)) {
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#if defined(TARGET_SPARC64) && !defined(TARGET_ABI32)
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                env->xcc |= PSR_CARRY;
#else
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                env->psr |= PSR_CARRY;
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#endif
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                ret = -ret;
            } else {
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#if defined(TARGET_SPARC64) && !defined(TARGET_ABI32)
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                env->xcc &= ~PSR_CARRY;
#else
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                env->psr &= ~PSR_CARRY;
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#endif
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            }
            env->regwptr[0] = ret;
            /* next instruction */
            env->pc = env->npc;
            env->npc = env->npc + 4;
            break;
        case 0x83: /* flush windows */
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#ifdef TARGET_ABI32
        case 0x103:
#endif
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            flush_windows(env);
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            /* next instruction */
            env->pc = env->npc;
            env->npc = env->npc + 4;
            break;
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#ifndef TARGET_SPARC64
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        case TT_WIN_OVF: /* window overflow */
            save_window(env);
            break;
        case TT_WIN_UNF: /* window underflow */
            restore_window(env);
            break;
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        case TT_TFAULT:
        case TT_DFAULT:
            {
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                info.si_signo = TARGET_SIGSEGV;
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                info.si_errno = 0;
                /* XXX: check env->error_code */
                info.si_code = TARGET_SEGV_MAPERR;
                info._sifields._sigfault._addr = env->mmuregs[4];
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                queue_signal(env, info.si_signo, &info);
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            }
            break;
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#else
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        case TT_SPILL: /* window overflow */
            save_window(env);
            break;
        case TT_FILL: /* window underflow */
            restore_window(env);
            break;
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        case TT_TFAULT:
        case TT_DFAULT:
            {
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                info.si_signo = TARGET_SIGSEGV;
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                info.si_errno = 0;
                /* XXX: check env->error_code */
                info.si_code = TARGET_SEGV_MAPERR;
                if (trapnr == TT_DFAULT)
                    info._sifields._sigfault._addr = env->dmmuregs[4];
                else
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                    info._sifields._sigfault._addr = cpu_tsptr(env)->tpc;
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                queue_signal(env, info.si_signo, &info);
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            }
            break;