gdbstub.c 75.9 KB
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/*
 * gdb server stub
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 *
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 * Copyright (c) 2003-2005 Fabrice Bellard
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 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
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 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
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 */
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#include "config.h"
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#include "qemu-common.h"
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#ifdef CONFIG_USER_ONLY
#include <stdlib.h>
#include <stdio.h>
#include <stdarg.h>
#include <string.h>
#include <errno.h>
#include <unistd.h>
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#include <fcntl.h>
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#include "qemu.h"
#else
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#include "monitor.h"
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#include "qemu-char.h"
#include "sysemu.h"
#include "gdbstub.h"
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#endif
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#define MAX_PACKET_LENGTH 4096

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#include "cpu.h"
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#include "qemu_socket.h"
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#include "kvm.h"
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#ifndef TARGET_CPU_MEMORY_RW_DEBUG
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static inline int target_memory_rw_debug(CPUArchState *env, target_ulong addr,
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                                         uint8_t *buf, int len, int is_write)
{
    return cpu_memory_rw_debug(env, addr, buf, len, is_write);
}
#else
/* target_memory_rw_debug() defined in cpu.h */
#endif
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enum {
    GDB_SIGNAL_0 = 0,
    GDB_SIGNAL_INT = 2,
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    GDB_SIGNAL_QUIT = 3,
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    GDB_SIGNAL_TRAP = 5,
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    GDB_SIGNAL_ABRT = 6,
    GDB_SIGNAL_ALRM = 14,
    GDB_SIGNAL_IO = 23,
    GDB_SIGNAL_XCPU = 24,
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    GDB_SIGNAL_UNKNOWN = 143
};

#ifdef CONFIG_USER_ONLY

/* Map target signal numbers to GDB protocol signal numbers and vice
 * versa.  For user emulation's currently supported systems, we can
 * assume most signals are defined.
 */

static int gdb_signal_table[] = {
    0,
    TARGET_SIGHUP,
    TARGET_SIGINT,
    TARGET_SIGQUIT,
    TARGET_SIGILL,
    TARGET_SIGTRAP,
    TARGET_SIGABRT,
    -1, /* SIGEMT */
    TARGET_SIGFPE,
    TARGET_SIGKILL,
    TARGET_SIGBUS,
    TARGET_SIGSEGV,
    TARGET_SIGSYS,
    TARGET_SIGPIPE,
    TARGET_SIGALRM,
    TARGET_SIGTERM,
    TARGET_SIGURG,
    TARGET_SIGSTOP,
    TARGET_SIGTSTP,
    TARGET_SIGCONT,
    TARGET_SIGCHLD,
    TARGET_SIGTTIN,
    TARGET_SIGTTOU,
    TARGET_SIGIO,
    TARGET_SIGXCPU,
    TARGET_SIGXFSZ,
    TARGET_SIGVTALRM,
    TARGET_SIGPROF,
    TARGET_SIGWINCH,
    -1, /* SIGLOST */
    TARGET_SIGUSR1,
    TARGET_SIGUSR2,
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#ifdef TARGET_SIGPWR
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    TARGET_SIGPWR,
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#else
    -1,
#endif
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    -1, /* SIGPOLL */
    -1,
    -1,
    -1,
    -1,
    -1,
    -1,
    -1,
    -1,
    -1,
    -1,
    -1,
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#ifdef __SIGRTMIN
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    __SIGRTMIN + 1,
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    -1, /* SIGCANCEL */
    __SIGRTMIN,
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    -1, /* SIGINFO */
    -1, /* UNKNOWN */
    -1, /* DEFAULT */
    -1,
    -1,
    -1,
    -1,
    -1,
    -1
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#endif
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};
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#else
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/* In system mode we only need SIGINT and SIGTRAP; other signals
   are not yet supported.  */

enum {
    TARGET_SIGINT = 2,
    TARGET_SIGTRAP = 5
};

static int gdb_signal_table[] = {
    -1,
    -1,
    TARGET_SIGINT,
    -1,
    -1,
    TARGET_SIGTRAP
};
#endif

#ifdef CONFIG_USER_ONLY
static int target_signal_to_gdb (int sig)
{
    int i;
    for (i = 0; i < ARRAY_SIZE (gdb_signal_table); i++)
        if (gdb_signal_table[i] == sig)
            return i;
    return GDB_SIGNAL_UNKNOWN;
}
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#endif
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static int gdb_signal_to_target (int sig)
{
    if (sig < ARRAY_SIZE (gdb_signal_table))
        return gdb_signal_table[sig];
    else
        return -1;
}

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//#define DEBUG_GDB
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typedef struct GDBRegisterState {
    int base_reg;
    int num_regs;
    gdb_reg_cb get_reg;
    gdb_reg_cb set_reg;
    const char *xml;
    struct GDBRegisterState *next;
} GDBRegisterState;

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enum RSState {
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    RS_INACTIVE,
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    RS_IDLE,
    RS_GETLINE,
    RS_CHKSUM1,
    RS_CHKSUM2,
};
typedef struct GDBState {
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    CPUArchState *c_cpu; /* current CPU for step/continue ops */
    CPUArchState *g_cpu; /* current CPU for other ops */
    CPUArchState *query_cpu; /* for q{f|s}ThreadInfo */
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    enum RSState state; /* parsing state */
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    char line_buf[MAX_PACKET_LENGTH];
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    int line_buf_index;
    int line_csum;
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    uint8_t last_packet[MAX_PACKET_LENGTH + 4];
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    int last_packet_len;
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    int signal;
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#ifdef CONFIG_USER_ONLY
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    int fd;
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    int running_state;
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#else
    CharDriverState *chr;
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    CharDriverState *mon_chr;
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#endif
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    char syscall_buf[256];
    gdb_syscall_complete_cb current_syscall_cb;
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} GDBState;
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/* By default use no IRQs and no timers while single stepping so as to
 * make single stepping like an ICE HW step.
 */
static int sstep_flags = SSTEP_ENABLE|SSTEP_NOIRQ|SSTEP_NOTIMER;

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static GDBState *gdbserver_state;

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/* This is an ugly hack to cope with both new and old gdb.
   If gdb sends qXfer:features:read then assume we're talking to a newish
   gdb that understands target descriptions.  */
static int gdb_has_xml;

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#ifdef CONFIG_USER_ONLY
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/* XXX: This is not thread safe.  Do we care?  */
static int gdbserver_fd = -1;

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static int get_char(GDBState *s)
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{
    uint8_t ch;
    int ret;

    for(;;) {
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        ret = qemu_recv(s->fd, &ch, 1, 0);
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        if (ret < 0) {
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            if (errno == ECONNRESET)
                s->fd = -1;
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            if (errno != EINTR && errno != EAGAIN)
                return -1;
        } else if (ret == 0) {
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            close(s->fd);
            s->fd = -1;
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            return -1;
        } else {
            break;
        }
    }
    return ch;
}
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#endif
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static enum {
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    GDB_SYS_UNKNOWN,
    GDB_SYS_ENABLED,
    GDB_SYS_DISABLED,
} gdb_syscall_mode;

/* If gdb is connected when the first semihosting syscall occurs then use
   remote gdb syscalls.  Otherwise use native file IO.  */
int use_gdb_syscalls(void)
{
    if (gdb_syscall_mode == GDB_SYS_UNKNOWN) {
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        gdb_syscall_mode = (gdbserver_state ? GDB_SYS_ENABLED
                                            : GDB_SYS_DISABLED);
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    }
    return gdb_syscall_mode == GDB_SYS_ENABLED;
}

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/* Resume execution.  */
static inline void gdb_continue(GDBState *s)
{
#ifdef CONFIG_USER_ONLY
    s->running_state = 1;
#else
    vm_start();
#endif
}

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static void put_buffer(GDBState *s, const uint8_t *buf, int len)
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{
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#ifdef CONFIG_USER_ONLY
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    int ret;

    while (len > 0) {
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        ret = send(s->fd, buf, len, 0);
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        if (ret < 0) {
            if (errno != EINTR && errno != EAGAIN)
                return;
        } else {
            buf += ret;
            len -= ret;
        }
    }
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#else
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    qemu_chr_fe_write(s->chr, buf, len);
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#endif
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}

static inline int fromhex(int v)
{
    if (v >= '0' && v <= '9')
        return v - '0';
    else if (v >= 'A' && v <= 'F')
        return v - 'A' + 10;
    else if (v >= 'a' && v <= 'f')
        return v - 'a' + 10;
    else
        return 0;
}

static inline int tohex(int v)
{
    if (v < 10)
        return v + '0';
    else
        return v - 10 + 'a';
}

static void memtohex(char *buf, const uint8_t *mem, int len)
{
    int i, c;
    char *q;
    q = buf;
    for(i = 0; i < len; i++) {
        c = mem[i];
        *q++ = tohex(c >> 4);
        *q++ = tohex(c & 0xf);
    }
    *q = '\0';
}

static void hextomem(uint8_t *mem, const char *buf, int len)
{
    int i;

    for(i = 0; i < len; i++) {
        mem[i] = (fromhex(buf[0]) << 4) | fromhex(buf[1]);
        buf += 2;
    }
}

/* return -1 if error, 0 if OK */
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static int put_packet_binary(GDBState *s, const char *buf, int len)
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{
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    int csum, i;
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    uint8_t *p;
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    for(;;) {
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        p = s->last_packet;
        *(p++) = '$';
        memcpy(p, buf, len);
        p += len;
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        csum = 0;
        for(i = 0; i < len; i++) {
            csum += buf[i];
        }
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        *(p++) = '#';
        *(p++) = tohex((csum >> 4) & 0xf);
        *(p++) = tohex((csum) & 0xf);
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        s->last_packet_len = p - s->last_packet;
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        put_buffer(s, (uint8_t *)s->last_packet, s->last_packet_len);
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#ifdef CONFIG_USER_ONLY
        i = get_char(s);
        if (i < 0)
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            return -1;
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        if (i == '+')
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            break;
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#else
        break;
#endif
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    }
    return 0;
}

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/* return -1 if error, 0 if OK */
static int put_packet(GDBState *s, const char *buf)
{
#ifdef DEBUG_GDB
    printf("reply='%s'\n", buf);
#endif
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    return put_packet_binary(s, buf, strlen(buf));
}

/* The GDB remote protocol transfers values in target byte order.  This means
   we can use the raw memory access routines to access the value buffer.
   Conveniently, these also handle the case where the buffer is mis-aligned.
 */
#define GET_REG8(val) do { \
    stb_p(mem_buf, val); \
    return 1; \
    } while(0)
#define GET_REG16(val) do { \
    stw_p(mem_buf, val); \
    return 2; \
    } while(0)
#define GET_REG32(val) do { \
    stl_p(mem_buf, val); \
    return 4; \
    } while(0)
#define GET_REG64(val) do { \
    stq_p(mem_buf, val); \
    return 8; \
    } while(0)

#if TARGET_LONG_BITS == 64
#define GET_REGL(val) GET_REG64(val)
#define ldtul_p(addr) ldq_p(addr)
#else
#define GET_REGL(val) GET_REG32(val)
#define ldtul_p(addr) ldl_p(addr)
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#endif

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#if defined(TARGET_I386)
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#ifdef TARGET_X86_64
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static const int gpr_map[16] = {
    R_EAX, R_EBX, R_ECX, R_EDX, R_ESI, R_EDI, R_EBP, R_ESP,
    8, 9, 10, 11, 12, 13, 14, 15
};
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#else
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#define gpr_map gpr_map32
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#endif
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static const int gpr_map32[8] = { 0, 1, 2, 3, 4, 5, 6, 7 };
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#define NUM_CORE_REGS (CPU_NB_REGS * 2 + 25)

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#define IDX_IP_REG      CPU_NB_REGS
#define IDX_FLAGS_REG   (IDX_IP_REG + 1)
#define IDX_SEG_REGS    (IDX_FLAGS_REG + 1)
#define IDX_FP_REGS     (IDX_SEG_REGS + 6)
#define IDX_XMM_REGS    (IDX_FP_REGS + 16)
#define IDX_MXCSR_REG   (IDX_XMM_REGS + CPU_NB_REGS)

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static int cpu_gdb_read_register(CPUX86State *env, uint8_t *mem_buf, int n)
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{
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    if (n < CPU_NB_REGS) {
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        if (TARGET_LONG_BITS == 64 && env->hflags & HF_CS64_MASK) {
            GET_REG64(env->regs[gpr_map[n]]);
        } else if (n < CPU_NB_REGS32) {
            GET_REG32(env->regs[gpr_map32[n]]);
        }
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    } else if (n >= IDX_FP_REGS && n < IDX_FP_REGS + 8) {
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#ifdef USE_X86LDOUBLE
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        /* FIXME: byteswap float values - after fixing fpregs layout. */
        memcpy(mem_buf, &env->fpregs[n - IDX_FP_REGS], 10);
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#else
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        memset(mem_buf, 0, 10);
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#endif
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        return 10;
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    } else if (n >= IDX_XMM_REGS && n < IDX_XMM_REGS + CPU_NB_REGS) {
        n -= IDX_XMM_REGS;
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        if (n < CPU_NB_REGS32 ||
            (TARGET_LONG_BITS == 64 && env->hflags & HF_CS64_MASK)) {
            stq_p(mem_buf, env->xmm_regs[n].XMM_Q(0));
            stq_p(mem_buf + 8, env->xmm_regs[n].XMM_Q(1));
            return 16;
        }
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    } else {
        switch (n) {
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        case IDX_IP_REG:
            if (TARGET_LONG_BITS == 64 && env->hflags & HF_CS64_MASK) {
                GET_REG64(env->eip);
            } else {
                GET_REG32(env->eip);
            }
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        case IDX_FLAGS_REG: GET_REG32(env->eflags);

        case IDX_SEG_REGS:     GET_REG32(env->segs[R_CS].selector);
        case IDX_SEG_REGS + 1: GET_REG32(env->segs[R_SS].selector);
        case IDX_SEG_REGS + 2: GET_REG32(env->segs[R_DS].selector);
        case IDX_SEG_REGS + 3: GET_REG32(env->segs[R_ES].selector);
        case IDX_SEG_REGS + 4: GET_REG32(env->segs[R_FS].selector);
        case IDX_SEG_REGS + 5: GET_REG32(env->segs[R_GS].selector);

        case IDX_FP_REGS + 8:  GET_REG32(env->fpuc);
        case IDX_FP_REGS + 9:  GET_REG32((env->fpus & ~0x3800) |
                                         (env->fpstt & 0x7) << 11);
        case IDX_FP_REGS + 10: GET_REG32(0); /* ftag */
        case IDX_FP_REGS + 11: GET_REG32(0); /* fiseg */
        case IDX_FP_REGS + 12: GET_REG32(0); /* fioff */
        case IDX_FP_REGS + 13: GET_REG32(0); /* foseg */
        case IDX_FP_REGS + 14: GET_REG32(0); /* fooff */
        case IDX_FP_REGS + 15: GET_REG32(0); /* fop */

        case IDX_MXCSR_REG: GET_REG32(env->mxcsr);
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        }
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    }
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    return 0;
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}

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static int cpu_x86_gdb_load_seg(CPUX86State *env, int sreg, uint8_t *mem_buf)
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{
    uint16_t selector = ldl_p(mem_buf);

    if (selector != env->segs[sreg].selector) {
#if defined(CONFIG_USER_ONLY)
        cpu_x86_load_seg(env, sreg, selector);
#else
        unsigned int limit, flags;
        target_ulong base;

        if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK)) {
            base = selector << 4;
            limit = 0xffff;
            flags = 0;
        } else {
            if (!cpu_x86_get_descr_debug(env, selector, &base, &limit, &flags))
                return 4;
        }
        cpu_x86_load_seg_cache(env, sreg, selector, base, limit, flags);
#endif
    }
    return 4;
}

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static int cpu_gdb_write_register(CPUX86State *env, uint8_t *mem_buf, int n)
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{
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    uint32_t tmp;
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    if (n < CPU_NB_REGS) {
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        if (TARGET_LONG_BITS == 64 && env->hflags & HF_CS64_MASK) {
            env->regs[gpr_map[n]] = ldtul_p(mem_buf);
            return sizeof(target_ulong);
        } else if (n < CPU_NB_REGS32) {
            n = gpr_map32[n];
            env->regs[n] &= ~0xffffffffUL;
            env->regs[n] |= (uint32_t)ldl_p(mem_buf);
            return 4;
        }
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    } else if (n >= IDX_FP_REGS && n < IDX_FP_REGS + 8) {
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#ifdef USE_X86LDOUBLE
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        /* FIXME: byteswap float values - after fixing fpregs layout. */
        memcpy(&env->fpregs[n - IDX_FP_REGS], mem_buf, 10);
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#endif
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        return 10;
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    } else if (n >= IDX_XMM_REGS && n < IDX_XMM_REGS + CPU_NB_REGS) {
        n -= IDX_XMM_REGS;
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        if (n < CPU_NB_REGS32 ||
            (TARGET_LONG_BITS == 64 && env->hflags & HF_CS64_MASK)) {
            env->xmm_regs[n].XMM_Q(0) = ldq_p(mem_buf);
            env->xmm_regs[n].XMM_Q(1) = ldq_p(mem_buf + 8);
            return 16;
        }
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    } else {
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        switch (n) {
        case IDX_IP_REG:
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            if (TARGET_LONG_BITS == 64 && env->hflags & HF_CS64_MASK) {
                env->eip = ldq_p(mem_buf);
                return 8;
            } else {
                env->eip &= ~0xffffffffUL;
                env->eip |= (uint32_t)ldl_p(mem_buf);
                return 4;
            }
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        case IDX_FLAGS_REG:
            env->eflags = ldl_p(mem_buf);
            return 4;

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        case IDX_SEG_REGS:     return cpu_x86_gdb_load_seg(env, R_CS, mem_buf);
        case IDX_SEG_REGS + 1: return cpu_x86_gdb_load_seg(env, R_SS, mem_buf);
        case IDX_SEG_REGS + 2: return cpu_x86_gdb_load_seg(env, R_DS, mem_buf);
        case IDX_SEG_REGS + 3: return cpu_x86_gdb_load_seg(env, R_ES, mem_buf);
        case IDX_SEG_REGS + 4: return cpu_x86_gdb_load_seg(env, R_FS, mem_buf);
        case IDX_SEG_REGS + 5: return cpu_x86_gdb_load_seg(env, R_GS, mem_buf);
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        case IDX_FP_REGS + 8:
            env->fpuc = ldl_p(mem_buf);
            return 4;
        case IDX_FP_REGS + 9:
            tmp = ldl_p(mem_buf);
            env->fpstt = (tmp >> 11) & 7;
            env->fpus = tmp & ~0x3800;
            return 4;
        case IDX_FP_REGS + 10: /* ftag */  return 4;
        case IDX_FP_REGS + 11: /* fiseg */ return 4;
        case IDX_FP_REGS + 12: /* fioff */ return 4;
        case IDX_FP_REGS + 13: /* foseg */ return 4;
        case IDX_FP_REGS + 14: /* fooff */ return 4;
        case IDX_FP_REGS + 15: /* fop */   return 4;

        case IDX_MXCSR_REG:
            env->mxcsr = ldl_p(mem_buf);
            return 4;
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        }
    }
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    /* Unrecognised register.  */
    return 0;
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}

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#elif defined (TARGET_PPC)

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/* Old gdb always expects FP registers.  Newer (xml-aware) gdb only
   expects whatever the target description contains.  Due to a
   historical mishap the FP registers appear in between core integer
   regs and PC, MSR, CR, and so forth.  We hack round this by giving the
   FP regs zero size when talking to a newer gdb.  */
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#define NUM_CORE_REGS 71
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#if defined (TARGET_PPC64)
#define GDB_CORE_XML "power64-core.xml"
#else
#define GDB_CORE_XML "power-core.xml"
#endif
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static int cpu_gdb_read_register(CPUPPCState *env, uint8_t *mem_buf, int n)
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{
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    if (n < 32) {
        /* gprs */
        GET_REGL(env->gpr[n]);
    } else if (n < 64) {
        /* fprs */
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        if (gdb_has_xml)
            return 0;
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        stfq_p(mem_buf, env->fpr[n-32]);
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        return 8;
    } else {
        switch (n) {
        case 64: GET_REGL(env->nip);
        case 65: GET_REGL(env->msr);
        case 66:
            {
                uint32_t cr = 0;
                int i;
                for (i = 0; i < 8; i++)
                    cr |= env->crf[i] << (32 - ((i + 1) * 4));
                GET_REG32(cr);
            }
        case 67: GET_REGL(env->lr);
        case 68: GET_REGL(env->ctr);
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        case 69: GET_REGL(env->xer);
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        case 70:
            {
                if (gdb_has_xml)
                    return 0;
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                GET_REG32(env->fpscr);
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            }
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        }
    }
    return 0;
}
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static int cpu_gdb_write_register(CPUPPCState *env, uint8_t *mem_buf, int n)
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{
    if (n < 32) {
        /* gprs */
        env->gpr[n] = ldtul_p(mem_buf);
        return sizeof(target_ulong);
    } else if (n < 64) {
        /* fprs */
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        if (gdb_has_xml)
            return 0;
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        env->fpr[n-32] = ldfq_p(mem_buf);
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        return 8;
    } else {
        switch (n) {
        case 64:
            env->nip = ldtul_p(mem_buf);
            return sizeof(target_ulong);
        case 65:
            ppc_store_msr(env, ldtul_p(mem_buf));
            return sizeof(target_ulong);
        case 66:
            {
                uint32_t cr = ldl_p(mem_buf);
                int i;
                for (i = 0; i < 8; i++)
                    env->crf[i] = (cr >> (32 - ((i + 1) * 4))) & 0xF;
                return 4;
            }
        case 67:
            env->lr = ldtul_p(mem_buf);
            return sizeof(target_ulong);
        case 68:
            env->ctr = ldtul_p(mem_buf);
            return sizeof(target_ulong);
        case 69:
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            env->xer = ldtul_p(mem_buf);
            return sizeof(target_ulong);
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        case 70:
            /* fpscr */
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            if (gdb_has_xml)
                return 0;
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            return 4;
        }
    }
    return 0;
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}
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#elif defined (TARGET_SPARC)
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#if defined(TARGET_SPARC64) && !defined(TARGET_ABI32)
#define NUM_CORE_REGS 86
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#else
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#define NUM_CORE_REGS 72
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#endif
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#ifdef TARGET_ABI32
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#define GET_REGA(val) GET_REG32(val)
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#else
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#define GET_REGA(val) GET_REGL(val)
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#endif
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static int cpu_gdb_read_register(CPUSPARCState *env, uint8_t *mem_buf, int n)
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{
    if (n < 8) {
        /* g0..g7 */
        GET_REGA(env->gregs[n]);
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    }
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    if (n < 32) {
        /* register window */
        GET_REGA(env->regwptr[n - 8]);
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    }
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#if defined(TARGET_ABI32) || !defined(TARGET_SPARC64)
    if (n < 64) {
        /* fprs */
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        if (n & 1) {
            GET_REG32(env->fpr[(n - 32) / 2].l.lower);
        } else {
            GET_REG32(env->fpr[(n - 32) / 2].l.upper);
        }
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    }
    /* Y, PSR, WIM, TBR, PC, NPC, FPSR, CPSR */
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    switch (n) {
    case 64: GET_REGA(env->y);
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    case 65: GET_REGA(cpu_get_psr(env));
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    case 66: GET_REGA(env->wim);
    case 67: GET_REGA(env->tbr);
    case 68: GET_REGA(env->pc);
    case 69: GET_REGA(env->npc);
    case 70: GET_REGA(env->fsr);
    case 71: GET_REGA(0); /* csr */
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    default: GET_REGA(0);
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    }
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#else
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    if (n < 64) {
        /* f0-f31 */
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        if (n & 1) {
            GET_REG32(env->fpr[(n - 32) / 2].l.lower);
        } else {
            GET_REG32(env->fpr[(n - 32) / 2].l.upper);
        }
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    }
    if (n < 80) {
        /* f32-f62 (double width, even numbers only) */
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        GET_REG64(env->fpr[(n - 32) / 2].ll);
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    }
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    switch (n) {
    case 80: GET_REGL(env->pc);
    case 81: GET_REGL(env->npc);
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    case 82: GET_REGL((cpu_get_ccr(env) << 32) |
                      ((env->asi & 0xff) << 24) |
                      ((env->pstate & 0xfff) << 8) |
                      cpu_get_cwp64(env));
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    case 83: GET_REGL(env->fsr);
    case 84: GET_REGL(env->fprs);
    case 85: GET_REGL(env->y);
    }
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#endif
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    return 0;
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}

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static int cpu_gdb_write_register(CPUSPARCState *env, uint8_t *mem_buf, int n)
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{
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#if defined(TARGET_ABI32)
    abi_ulong tmp;

    tmp = ldl_p(mem_buf);
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#else
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    target_ulong tmp;

    tmp = ldtul_p(mem_buf);
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#endif
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    if (n < 8) {
        /* g0..g7 */
        env->gregs[n] = tmp;
    } else if (n < 32) {
        /* register window */
        env->regwptr[n - 8] = tmp;
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    }
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#if defined(TARGET_ABI32) || !defined(TARGET_SPARC64)
    else if (n < 64) {
        /* fprs */
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        /* f0-f31 */
        if (n & 1) {
            env->fpr[(n - 32) / 2].l.lower = tmp;
        } else {
            env->fpr[(n - 32) / 2].l.upper = tmp;
        }
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    } else {
        /* Y, PSR, WIM, TBR, PC, NPC, FPSR, CPSR */
        switch (n) {
        case 64: env->y = tmp; break;
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        case 65: cpu_put_psr(env, tmp); break;
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        case 66: env->wim = tmp; break;
        case 67: env->tbr = tmp; break;
        case 68: env->pc = tmp; break;
        case 69: env->npc = tmp; break;
        case 70: env->fsr = tmp; break;
        default: return 0;
        }
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    }
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    return 4;
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#else
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    else if (n < 64) {
        /* f0-f31 */
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        tmp = ldl_p(mem_buf);
        if (n & 1) {
            env->fpr[(n - 32) / 2].l.lower = tmp;
        } else {
            env->fpr[(n - 32) / 2].l.upper = tmp;
        }
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        return 4;
    } else if (n < 80) {
        /* f32-f62 (double width, even numbers only) */
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        env->fpr[(n - 32) / 2].ll = tmp;
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    } else {
        switch (n) {
        case 80: env->pc = tmp; break;
        case 81: env->npc = tmp; break;
        case 82:
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            cpu_put_ccr(env, tmp >> 32);
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	    env->asi = (tmp >> 24) & 0xff;
	    env->pstate = (tmp >> 8) & 0xfff;
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            cpu_put_cwp64(env, tmp & 0xff);
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	    break;
        case 83: env->fsr = tmp; break;
        case 84: env->fprs = tmp; break;
        case 85: env->y = tmp; break;
        default: return 0;
        }
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    }
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    return 8;
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#endif
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}
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#elif defined (TARGET_ARM)
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/* Old gdb always expect FPA registers.  Newer (xml-aware) gdb only expect
   whatever the target description contains.  Due to a historical mishap
   the FPA registers appear in between core integer regs and the CPSR.
   We hack round this by giving the FPA regs zero size when talking to a
   newer gdb.  */
#define NUM_CORE_REGS 26
#define GDB_CORE_XML "arm-core.xml"
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static int cpu_gdb_read_register(CPUARMState *env, uint8_t *mem_buf, int n)
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{
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    if (n < 16) {
        /* Core integer register.  */
        GET_REG32(env->regs[n]);
    }
    if (n < 24) {
        /* FPA registers.  */
        if (gdb_has_xml)
            return 0;
        memset(mem_buf, 0, 12);
        return 12;
    }
    switch (n) {
    case 24:
        /* FPA status register.  */
        if (gdb_has_xml)
            return 0;
        GET_REG32(0);
    case 25:
        /* CPSR */
        GET_REG32(cpsr_read(env));
    }
    /* Unknown register.  */
    return 0;
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}
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static int cpu_gdb_write_register(CPUARMState *env, uint8_t *mem_buf, int n)
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{
    uint32_t tmp;
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    tmp = ldl_p(mem_buf);
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    /* Mask out low bit of PC to workaround gdb bugs.  This will probably
       cause problems if we ever implement the Jazelle DBX extensions.  */
    if (n == 15)
        tmp &= ~1;
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    if (n < 16) {
        /* Core integer register.  */
        env->regs[n] = tmp;
        return 4;
    }
    if (n < 24) { /* 16-23 */
        /* FPA registers (ignored).  */
        if (gdb_has_xml)
            return 0;
        return 12;
    }
    switch (n) {
    case 24:
        /* FPA status register (ignored).  */
        if (gdb_has_xml)
            return 0;
        return 4;
    case 25:
        /* CPSR */
        cpsr_write (env, tmp, 0xffffffff);
        return 4;
    }
    /* Unknown register.  */
    return 0;
}
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#elif defined (TARGET_M68K)
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#define NUM_CORE_REGS 18
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#define GDB_CORE_XML "cf-core.xml"
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static int cpu_gdb_read_register(CPUM68KState *env, uint8_t *mem_buf, int n)
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{
    if (n < 8) {
        /* D0-D7 */
        GET_REG32(env->dregs[n]);
    } else if (n < 16) {
        /* A0-A7 */
        GET_REG32(env->aregs[n - 8]);
    } else {
	switch (n) {
        case 16: GET_REG32(env->sr);
        case 17: GET_REG32(env->pc);
        }
    }
    /* FP registers not included here because they vary between
       ColdFire and m68k.  Use XML bits for these.  */
    return 0;
}
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static int cpu_gdb_write_register(CPUM68KState *env, uint8_t *mem_buf, int n)
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{
    uint32_t tmp;
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    tmp = ldl_p(mem_buf);
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    if (n < 8) {
        /* D0-D7 */
        env->dregs[n] = tmp;
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    } else if (n < 16) {
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        /* A0-A7 */
        env->aregs[n - 8] = tmp;
    } else {
        switch (n) {
        case 16: env->sr = tmp; break;
        case 17: env->pc = tmp; break;
        default: return 0;
        }
    }
    return 4;
}
#elif defined (TARGET_MIPS)
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#define NUM_CORE_REGS 73
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static int cpu_gdb_read_register(CPUMIPSState *env, uint8_t *mem_buf, int n)
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{
    if (n < 32) {
        GET_REGL(env->active_tc.gpr[n]);
    }
    if (env->CP0_Config1 & (1 << CP0C1_FP)) {
        if (n >= 38 && n < 70) {
            if (env->CP0_Status & (1 << CP0St_FR))
		GET_REGL(env->active_fpu.fpr[n - 38].d);
            else
		GET_REGL(env->active_fpu.fpr[n - 38].w[FP_ENDIAN_IDX]);
        }
        switch (n) {
        case 70: GET_REGL((int32_t)env->active_fpu.fcr31);
        case 71: GET_REGL((int32_t)env->active_fpu.fcr0);
        }
    }
    switch (n) {
    case 32: GET_REGL((int32_t)env->CP0_Status);
    case 33: GET_REGL(env->active_tc.LO[0]);
    case 34: GET_REGL(env->active_tc.HI[0]);
    case 35: GET_REGL(env->CP0_BadVAddr);
    case 36: GET_REGL((int32_t)env->CP0_Cause);
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    case 37: GET_REGL(env->active_tc.PC | !!(env->hflags & MIPS_HFLAG_M16));
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    case 72: GET_REGL(0); /* fp */
    case 89: GET_REGL((int32_t)env->CP0_PRid);
    }
    if (n >= 73 && n <= 88) {
	/* 16 embedded regs.  */
	GET_REGL(0);
    }
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    return 0;
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}

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/* convert MIPS rounding mode in FCR31 to IEEE library */
static unsigned int ieee_rm[] =
  {
    float_round_nearest_even,
    float_round_to_zero,
    float_round_up,
    float_round_down
  };
#define RESTORE_ROUNDING_MODE \
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    set_float_rounding_mode(ieee_rm[env->active_fpu.fcr31 & 3], &env->active_fpu.fp_status)
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static int cpu_gdb_write_register(CPUMIPSState *env, uint8_t *mem_buf, int n)
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{
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    target_ulong tmp;
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    tmp = ldtul_p(mem_buf);
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    if (n < 32) {
        env->active_tc.gpr[n] = tmp;
        return sizeof(target_ulong);
    }
    if (env->CP0_Config1 & (1 << CP0C1_FP)
            && n >= 38 && n < 73) {
        if (n < 70) {
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            if (env->CP0_Status & (1 << CP0St_FR))
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              env->active_fpu.fpr[n - 38].d = tmp;
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            else
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              env->active_fpu.fpr[n - 38].w[FP_ENDIAN_IDX] = tmp;
        }
        switch (n) {
        case 70:
            env->active_fpu.fcr31 = tmp & 0xFF83FFFF;
            /* set rounding mode */
            RESTORE_ROUNDING_MODE;
            break;
        case 71: env->active_fpu.fcr0 = tmp; break;
        }
        return sizeof(target_ulong);
    }
    switch (n) {
    case 32: env->CP0_Status = tmp; break;
    case 33: env->active_tc.LO[0] = tmp; break;
    case 34: env->active_tc.HI[0] = tmp; break;
    case 35: env->CP0_BadVAddr = tmp; break;
    case 36: env->CP0_Cause = tmp; break;
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    case 37:
        env->active_tc.PC = tmp & ~(target_ulong)1;
        if (tmp & 1) {
            env->hflags |= MIPS_HFLAG_M16;
        } else {
            env->hflags &= ~(MIPS_HFLAG_M16);
        }
        break;
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    case 72: /* fp, ignored */ break;
    default: 
	if (n > 89)
	    return 0;
	/* Other registers are readonly.  Ignore writes.  */
	break;
    }

    return sizeof(target_ulong);
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}
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#elif defined(TARGET_OPENRISC)

#define NUM_CORE_REGS (32 + 3)

static int cpu_gdb_read_register(CPUOpenRISCState *env, uint8_t *mem_buf, int n)
{
    if (n < 32) {
        GET_REG32(env->gpr[n]);
    } else {
        switch (n) {
        case 32:    /* PPC */
            GET_REG32(env->ppc);
            break;

        case 33:    /* NPC */
            GET_REG32(env->npc);
            break;

        case 34:    /* SR */
            GET_REG32(env->sr);
            break;

        default:
            break;
        }
    }
    return 0;
}

static int cpu_gdb_write_register(CPUOpenRISCState *env,
                                  uint8_t *mem_buf, int n)
{
    uint32_t tmp;

    if (n > NUM_CORE_REGS) {
        return 0;
    }

    tmp = ldl_p(mem_buf);

    if (n < 32) {
        env->gpr[n] = tmp;
    } else {
        switch (n) {
        case 32: /* PPC */
            env->ppc = tmp;
            break;

        case 33: /* NPC */
            env->npc = tmp;
            break;

        case 34: /* SR */
            env->sr = tmp;
            break;

        default:
            break;
        }
    }
    return 4;
}
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#elif defined (TARGET_SH4)
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/* Hint: Use "set architecture sh4" in GDB to see fpu registers */
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/* FIXME: We should use XML for this.  */

#define NUM_CORE_REGS 59
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static int cpu_gdb_read_register(CPUSH4State *env, uint8_t *mem_buf, int n)
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{
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    switch (n) {
    case 0 ... 7:
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        if ((env->sr & (SR_MD | SR_RB)) == (SR_MD | SR_RB)) {
            GET_REGL(env->gregs[n + 16]);
        } else {
            GET_REGL(env->gregs[n]);
        }
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    case 8 ... 15:
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        GET_REGL(env->gregs[n]);
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    case 16:
        GET_REGL(env->pc);
    case 17:
        GET_REGL(env->pr);
    case 18:
        GET_REGL(env->gbr);
    case 19:
        GET_REGL(env->vbr);
    case 20:
        GET_REGL(env->mach);
    case 21:
        GET_REGL(env->macl);
    case 22:
        GET_REGL(env->sr);
    case 23:
        GET_REGL(env->fpul);
    case 24:
        GET_REGL(env->fpscr);
    case 25 ... 40:
        if (env->fpscr & FPSCR_FR) {
            stfl_p(mem_buf, env->fregs[n - 9]);
        } else {
            stfl_p(mem_buf, env->fregs[n - 25]);
        }
        return 4;
    case 41:
        GET_REGL(env->ssr);
    case 42:
        GET_REGL(env->spc);
    case 43 ... 50:
        GET_REGL(env->gregs[n - 43]);
    case 51 ... 58:
        GET_REGL(env->gregs[n - (51 - 16)]);
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    }

    return 0;
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}

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static int cpu_gdb_write_register(CPUSH4State *env, uint8_t *mem_buf, int n)
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{
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    switch (n) {
    case 0 ... 7:
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        if ((env->sr & (SR_MD | SR_RB)) == (SR_MD | SR_RB)) {
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            env->gregs[n + 16] = ldl_p(mem_buf);
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        } else {
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            env->gregs[n] = ldl_p(mem_buf);
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        }
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        break;
    case 8 ... 15:
        env->gregs[n] = ldl_p(mem_buf);
        break;
    case 16:
        env->pc = ldl_p(mem_buf);
        break;
    case 17:
        env->pr = ldl_p(mem_buf);
        break;
    case 18:
        env->gbr = ldl_p(mem_buf);
        break;
    case 19:
        env->vbr = ldl_p(mem_buf);
        break;
    case 20:
        env->mach = ldl_p(mem_buf);
        break;
    case 21:
        env->macl = ldl_p(mem_buf);
        break;
    case 22:
        env->sr = ldl_p(mem_buf);
        break;
    case 23:
        env->fpul = ldl_p(mem_buf);
        break;
    case 24:
        env->fpscr = ldl_p(mem_buf);
        break;
    case 25 ... 40:
        if (env->fpscr & FPSCR_FR) {
            env->fregs[n - 9] = ldfl_p(mem_buf);
        } else {
            env->fregs[n - 25] = ldfl_p(mem_buf);
        }
        break;
    case 41:
        env->ssr = ldl_p(mem_buf);
        break;
    case 42:
        env->spc = ldl_p(mem_buf);
        break;
    case 43 ... 50:
        env->gregs[n - 43] = ldl_p(mem_buf);
        break;
    case 51 ... 58:
        env->gregs[n - (51 - 16)] = ldl_p(mem_buf);
        break;
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    default: return 0;
    }

    return 4;
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}
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#elif defined (TARGET_MICROBLAZE)

#define NUM_CORE_REGS (32 + 5)

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static int cpu_gdb_read_register(CPUMBState *env, uint8_t *mem_buf, int n)
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{
    if (n < 32) {
	GET_REG32(env->regs[n]);
    } else {
	GET_REG32(env->sregs[n - 32]);
    }
    return 0;
}

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static int cpu_gdb_write_register(CPUMBState *env, uint8_t *mem_buf, int n)
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{
    uint32_t tmp;

    if (n > NUM_CORE_REGS)
	return 0;

    tmp = ldl_p(mem_buf);

    if (n < 32) {
	env->regs[n] = tmp;
    } else {
	env->sregs[n - 32] = tmp;
    }
    return 4;
}
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#elif defined (TARGET_CRIS)

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#define NUM_CORE_REGS 49

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static int
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read_register_crisv10(CPUCRISState *env, uint8_t *mem_buf, int n)
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{
    if (n < 15) {
        GET_REG32(env->regs[n]);
    }

    if (n == 15) {
        GET_REG32(env->pc);
    }

    if (n < 32) {
        switch (n) {
        case 16:
            GET_REG8(env->pregs[n - 16]);
            break;
        case 17:
            GET_REG8(env->pregs[n - 16]);
            break;
        case 20:
        case 21:
            GET_REG16(env->pregs[n - 16]);
            break;
        default:
            if (n >= 23) {
                GET_REG32(env->pregs[n - 16]);
            }
            break;
        }
    }
    return 0;
}

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static int cpu_gdb_read_register(CPUCRISState *env, uint8_t *mem_buf, int n)
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{
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    uint8_t srs;

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    if (env->pregs[PR_VR] < 32)
        return read_register_crisv10(env, mem_buf, n);

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    srs = env->pregs[PR_SRS];
    if (n < 16) {
	GET_REG32(env->regs[n]);
    }

    if (n >= 21 && n < 32) {
	GET_REG32(env->pregs[n - 16]);
    }
    if (n >= 33 && n < 49) {
	GET_REG32(env->sregs[srs][n - 33]);
    }
    switch (n) {
    case 16: GET_REG8(env->pregs[0]);
    case 17: GET_REG8(env->pregs[1]);
    case 18: GET_REG32(env->pregs[2]);
    case 19: GET_REG8(srs);
    case 20: GET_REG16(env->pregs[4]);
    case 32: GET_REG32(env->pc);
    }

    return 0;
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}
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static int cpu_gdb_write_register(CPUCRISState *env, uint8_t *mem_buf, int n)
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{
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    uint32_t tmp;

    if (n > 49)
	return 0;

    tmp = ldl_p(mem_buf);

    if (n < 16) {
	env->regs[n] = tmp;
    }

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    if (n >= 21 && n < 32) {
	env->pregs[n - 16] = tmp;
    }

    /* FIXME: Should support function regs be writable?  */
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    switch (n) {
    case 16: return 1;
    case 17: return 1;
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    case 18: env->pregs[PR_PID] = tmp; break;
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    case 19: return 1;
    case 20: return 2;
    case 32: env->pc = tmp; break;
    }

    return 4;
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}
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#elif defined (TARGET_ALPHA)