1. 13 Apr, 2013 2 commits
  2. 14 Aug, 2012 1 commit
  3. 16 Jun, 2010 1 commit
    • Richard Henderson's avatar
      tcg: Optionally sign-extend 32-bit arguments for 64-bit hosts. · 2bece2c8
      Richard Henderson authored
      Some hosts (amd64, ia64) have an ABI that ignores the high bits
      of the 64-bit register when passing 32-bit arguments.  Others
      require the value to be properly sign-extended for the type.
      I.e. "int32_t" must be sign-extended and "uint32_t" must be
      zero-extended to 64-bits.
      To effect this, extend the "sizemask" parameter to tcg_gen_callN
      to include the signedness of the type of each parameter.  If the
      tcg target requires it, extend each 32-bit argument into a 64-bit
      temp and pass that to the function call.
      This ABI feature is required by sparc64, ppc64 and s390x.
      Signed-off-by: default avatarRichard Henderson <rth@twiddle.net>
      Signed-off-by: default avatarAurelien Jarno <aurelien@aurel32.net>
  4. 04 Oct, 2009 1 commit
    • Andre Przywara's avatar
      target-i386: add SSE4a instruction support · d9f4bb27
      Andre Przywara authored
      This adds support for the AMD Phenom/Barcelona's SSE4a instructions.
      Those include insertq and extrq, which are doing shift and mask on
      XMM registers, in two versions (immediate shift/length values and
      stored in another XMM register).
      Additionally it implements movntss, movntsd, which are scalar
      non-temporal stores (avoiding cache trashing). These are implemented
      as normal stores, though.
      SSE4a is guarded by the SSE4A CPUID bit (Fn8000_0001:ECX[6]).
      Signed-off-by: default avatarAndre Przywara <andre.przywara@amd.com>
      Signed-off-by: default avatarAurelien Jarno <aurelien@aurel32.net>
  5. 16 Jul, 2009 1 commit
  6. 04 Jan, 2009 1 commit
  7. 17 Nov, 2008 1 commit
  8. 03 Oct, 2008 1 commit
  9. 25 Sep, 2008 1 commit
  10. 22 May, 2008 1 commit
  11. 15 May, 2008 1 commit
  12. 12 May, 2008 1 commit