1. 05 May, 2011 14 commits
  2. 07 Apr, 2011 12 commits
  3. 06 Apr, 2011 3 commits
  4. 01 Apr, 2011 4 commits
    • Isaku Yamahata's avatar
      piix_pci: load path clean up · afe3ef1d
      Isaku Yamahata authored
      
      
      The previous patch didn't change the behavior when load,
      it resulted in ugly code. This patch cleans it up.
      
      With this patch, pic irq lines are manipulated when loaded.
      It is expected that it won't change the behaviour because
      the interrupts are level: at the moment e.g. pci devices already
      reassert interrupts on load.
      
      Test:
      - rung linux as guest and use flooding ping (ping -f) to host
        in order to trigger interrupts for e1000 emulated.
      - savevm/loadvm and see guest kept running after loadvm.
      
      To be honest, I'm not sure that ping -f caused enough interrupts
      because Linux e1000 driver supports NAPI.
      TODO: test more OSes, stress test with save/load, live-migration
      Signed-off-by: default avatarIsaku Yamahata <yamahata@valinux.co.jp>
      Signed-off-by: default avatarMichael S. Tsirkin <mst@redhat.com>
      afe3ef1d
    • Isaku Yamahata's avatar
      piix_pci: optimize set irq path · ab431c28
      Isaku Yamahata authored
      
      
      optimize irq routing in piix_pic.c which has been a TODO.
      So far piix3 tracks each pirq level and checks whether a given pic pins is
      asserted by seeing if each pirq is mapped into the pic pin.
      This is independent on irq routing, but data path is on slow path.
      
      Given that irq routing is rarely changed and asserting pic pins is on
      data path, the path that asserts pic pins should be optimized and
      chainging irq routing should be on slow path.
      The new behavior with this patch series is to use bitmap which is addressed
      by pirq and pic pins with a given irq routing.
      When pirq is asserted, the bitmap is set and see if the pic pins is
      asserted by checking the bitmaps.
      When irq routing is changed, rebuild the bitmap and re-assert pic pins.
      
      test:
      - create VM with 4 e1000 nics in different pci slots
        (i.e. fn=0 for each e1000)
        Thus those e1000's INTA are connected to each PIRQ[A-D].
      - run linux as guest and saw each devices triggers interrupt
        by seeing /proc/interrupts. And then confirmed that each PIRQ[A-D]
        surely asserted interrupts.
        Because irq 10 and 11 are shared by 4 e1000's, it only one NIC is activated
        with ifconfig ethN up/down when counting interrupts.
      
      Cc: Michael S. Tsirkin <mst@redhat.com>
      Signed-off-by: default avatarIsaku Yamahata <yamahata@valinux.co.jp>
      Signed-off-by: default avatarMichael S. Tsirkin <mst@redhat.com>
      ab431c28
    • Isaku Yamahata's avatar
      piix_pci: eliminate PIIX3State::pci_irq_levels · e735b55a
      Isaku Yamahata authored
      
      
      PIIX3State::pci_irq_levels are redundant which is already tracked by
      PCIBus layer. So eliminate them.
      
      Cc: Juan Quintela <quintela@redhat.com>
      Cc: Michael S. Tsirkin <mst@redhat.com>
      Signed-off-by: default avatarIsaku Yamahata <yamahata@valinux.co.jp>
      Signed-off-by: default avatarMichael S. Tsirkin <mst@redhat.com>
      e735b55a
    • Isaku Yamahata's avatar
      pci: add accessor function to get irq levels · 9ddf8437
      Isaku Yamahata authored
      
      
      Introduce accessor function to know INTx levels.
      It will be used later by q35.
      Although piix_pci tracks the intx line levels, it can be eliminated
      by this helper function.
      
      Cc: Michael S. Tsirkin <mst@redhat.com>
      Signed-off-by: default avatarIsaku Yamahata <yamahata@valinux.co.jp>
      Signed-off-by: default avatarMichael S. Tsirkin <mst@redhat.com>
      9ddf8437
  5. 28 Mar, 2011 7 commits