1. 22 Aug, 2013 28 commits
  2. 21 Aug, 2013 1 commit
  3. 20 Aug, 2013 11 commits
    • Anthony Liguori's avatar
      Merge remote-tracking branch 'pmaydell/tags/pull-target-arm-20130820' into staging · ecfe10c9
      Anthony Liguori authored
      target-arm queue
      
      # gpg: Signature made Tue 20 Aug 2013 08:56:28 AM CDT using RSA key ID 14360CDE
      # gpg: Can't check signature: public key not found
      
      # By Peter Maydell (20) and Peter Chubb (1)
      # Via Peter Maydell
      * pmaydell/tags/pull-target-arm-20130820: (21 commits)
        hw/timer/imx_epit: Simplify and fix imx_epit implementation
        default-configs: Fix A9MP and A15MP config names
        hw/cpu/a15mpcore: Wire generic timer outputs to GIC inputs
        target-arm: Implement the generic timer
        target-arm: Support coprocessor registers which do I/O
        target-arm: Allow raw_read() and raw_write() to handle 64 bit regs
        hw/arm/pic_cpu: Remove the now-unneeded arm_pic_init_cpu()
        hw/arm/xilinx_zynq: Don't use arm_pic_init_cpu()
        hw/arm/vexpress: Don't use arm_pic_init_cpu()
        hw/arm/versatilepb: Don't use arm_pic_init_cpu()
        hw/arm/strongarm: Don't use arm_pic_init_cpu()
        hw/arm/realview: Don't use arm_pic_init_cpu()
        hw/arm/omap*: Don't use arm_pic_init_cpu()
        hw/arm/musicpal: Don't use arm_pic_init_cpu()
        hw/arm/kzm: Don't use arm_pic_init_cpu()
        hw/arm/integratorcp: Don't use arm_pic_init_cpu()
        hw/arm/highbank: Don't use arm_pic_init_cpu()
        hw/arm/exynos4210: Don't use arm_pic_init_cpu()
        hw/arm/armv7m: Don't use arm_pic_init_cpu()
        target-arm: Make IRQ and FIQ gpio lines on the CPU object
        ...
      
      Message-id: 1377007680-4934-1-git-send-email-peter.maydell@linaro.org
      Signed-off-by: default avatarAnthony Liguori <anthony@codemonkey.ws>
      ecfe10c9
    • Anthony Liguori's avatar
      Merge remote-tracking branch 'stefanha/block-next' into staging · 9176e8fb
      Anthony Liguori authored
      # By Stefan Hajnoczi
      # Via Stefan Hajnoczi
      * stefanha/block-next:
        aio: drop io_flush argument
        tests: drop event_active_cb()
        thread-pool: drop thread_pool_active()
        dataplane/virtio-blk: drop flush_true() and flush_io()
        block/ssh: drop return_true()
        block/sheepdog: drop have_co_req() and aio_flush_request()
        block/rbd: drop qemu_rbd_aio_flush_cb()
        block/nbd: drop nbd_have_request()
        block/linux-aio: drop qemu_laio_completion_cb()
        block/iscsi: drop iscsi_process_flush()
        block/gluster: drop qemu_gluster_aio_flush_cb()
        block/curl: drop curl_aio_flush()
        aio: stop using .io_flush()
        tests: adjust test-thread-pool to new aio_poll() semantics
        tests: adjust test-aio to new aio_poll() semantics
        dataplane/virtio-blk: check exit conditions before aio_poll()
        block: stop relying on io_flush() in bdrv_drain_all()
        block: ensure bdrv_drain_all() works during bdrv_delete()
      
      Message-id: 1376921877-9576-1-git-send-email-stefanha@redhat.com
      Signed-off-by: default avatarAnthony Liguori <anthony@codemonkey.ws>
      9176e8fb
    • Anthony Liguori's avatar
      Merge remote-tracking branch 'rth/axp-next' into staging · 72420ce9
      Anthony Liguori authored
      # By Richard Henderson
      # Via Richard Henderson
      * rth/axp-next:
        target-alpha: Implement the typhoon iommu
        target-alpha: Consider the superpage when threading and ending TBs
        target-alpha: Use goto_tb in call_pal
        target-alpha: Implement call_pal without an exception
      
      Message-id: 1376720412-2165-1-git-send-email-rth@twiddle.net
      Signed-off-by: default avatarAnthony Liguori <anthony@codemonkey.ws>
      72420ce9
    • Anthony Liguori's avatar
      Merge remote-tracking branch 'afaerber/tags/qom-cpu-for-anthony' into staging · 237e4f92
      Anthony Liguori authored
      QOM CPUState refactorings / X86CPU
      
      * gdbstub coprocessor register count bugfix
      * QOM instance_post_init infrastructure to override dynamic properties
      * X86CPU HyperV preparations for CPU subclasses
      
      # gpg: Signature made Fri 16 Aug 2013 11:49:02 AM CDT using RSA key ID 3E7E013F
      # gpg: Can't check signature: public key not found
      
      # By Eduardo Habkost (3) and others
      # Via Andreas Färber
      * afaerber/tags/qom-cpu-for-anthony:
        cpus: Use cpu_is_stopped() efficiently
        target-i386: Move hyperv_* static globals to X86CPU
        qdev: Set globals in instance_post_init function
        qom: Introduce instance_post_init hook
        tests: Unit tests for qdev global properties handling
        gdbstub: Fix gdb_register_coprocessor() register counting
      237e4f92
    • Peter Chubb's avatar
      hw/timer/imx_epit: Simplify and fix imx_epit implementation · 23005810
      Peter Chubb authored
      When imx_epit.c was last refactored, a common usecase (comparison
      register zero) broke.  This patch fixes that, and simplifies the code
      yet more.  It also fixes a major thinko in the reset path --- the
      wrong bits in the control register were being cleared.
      Signed-off-by: default avatarPeter Chubb <peter.chubb@nicta.com.au>
      Reviewed-by: default avatarJean-Christophe DUBOIS <jcd@tribudubois.net>
      Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
      23005810
    • Peter Maydell's avatar
      default-configs: Fix A9MP and A15MP config names · 66aae5e1
      Peter Maydell authored
      When individual CONFIG_ switches for the A9MPcore and A15MPcore
      devices were created, they were inadvertently given incorrect names
      (CONFIG_ARM9MPCORE and CONFIG_ARM15MPCORE). These CPUs are
      "Cortex-A9MP" and "Cortex-A15MP", and in particular the ARM9 is
      a different (rather older) CPU than the Cortex-A9. Rename the
      CONFIG_ switches to bring them into line with the source file
      names and CPU names.
      Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
      Message-id: 1376056215-26391-1-git-send-email-peter.maydell@linaro.org
      66aae5e1
    • Peter Maydell's avatar
      hw/cpu/a15mpcore: Wire generic timer outputs to GIC inputs · 6033e840
      Peter Maydell authored
      Now our A15 CPU implements the generic timers, we can wire them
      up to the appropriate inputs on the GIC.
      Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
      Tested-by: default avatarLaurent Desnogues <laurent.desnogues@gmail.com>
      Message-id: 1376065080-26661-5-git-send-email-peter.maydell@linaro.org
      6033e840
    • Peter Maydell's avatar
      target-arm: Implement the generic timer · 55d284af
      Peter Maydell authored
      The ARMv7 architecture specifies a 'generic timer' which is implemented
      via cp15 registers. Newer kernels will prefer to use this rather than
      a devboard-level timer. Implement the generic timer for TCG; for KVM
      we will already use the hardware's virtualized timer for this.
      Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
      Tested-by: default avatarLaurent Desnogues <laurent.desnogues@gmail.com>
      Message-id: 1376065080-26661-4-git-send-email-peter.maydell@linaro.org
      55d284af
    • Peter Maydell's avatar
      target-arm: Support coprocessor registers which do I/O · 2452731c
      Peter Maydell authored
      Add an ARM_CP_IO flag which an ARMCPRegInfo definition can use to
      indicate that the register's implementation does I/O and thus
      its accesses need to be surrounded by gen_io_start()/gen_io_end()
      in order for icount to work. Most notably, cp registers which
      implement clocks or timers need this.
      Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
      Tested-by: default avatarLaurent Desnogues <laurent.desnogues@gmail.com>
      Reviewed-by: default avatarEdgar E. Iglesias <edgar.iglesias@gmail.com>
      Message-id: 1376065080-26661-3-git-send-email-peter.maydell@linaro.org
      2452731c
    • Peter Maydell's avatar
      target-arm: Allow raw_read() and raw_write() to handle 64 bit regs · 22d9e1a9
      Peter Maydell authored
      Extend the raw_read() and raw_write() helper accessors so that
      they can be used for 64 bit registers as well as 32 bit registers.
      Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
      Tested-by: default avatarLaurent Desnogues <laurent.desnogues@gmail.com>
      Reviewed-by: default avatarEdgar E. Iglesias <edgar.iglesias@gmail.com>
      Message-id: 1376065080-26661-2-git-send-email-peter.maydell@linaro.org
      22d9e1a9
    • Peter Maydell's avatar
      hw/arm/pic_cpu: Remove the now-unneeded arm_pic_init_cpu() · b643e4b9
      Peter Maydell authored
      Now all the boards have been converted arm_pic_init_cpu()
      is unused and can just be deleted.
      Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
      Message-id: 1375977856-25046-15-git-send-email-peter.maydell@linaro.org
      b643e4b9