1. 28 Aug, 2012 1 commit
  2. 24 Jun, 2012 1 commit
  3. 23 Jun, 2012 8 commits
  4. 15 Apr, 2012 1 commit
  5. 15 Mar, 2012 2 commits
  6. 14 Mar, 2012 1 commit
  7. 28 Feb, 2012 1 commit
  8. 01 Feb, 2012 6 commits
  9. 11 Nov, 2011 1 commit
  10. 30 Oct, 2011 1 commit
  11. 06 Oct, 2011 1 commit
  12. 23 Aug, 2011 1 commit
  13. 26 Jun, 2011 1 commit
  14. 16 Jun, 2011 1 commit
  15. 03 Jun, 2011 1 commit
  16. 11 May, 2011 2 commits
    • Alexander Graf's avatar
      PPC: Implement e500 (FSL) MMU · 01662f3e
      Alexander Graf authored
      Most of the code to support e500 style MMUs is already in place, but
      we're missing on some of the special TLB0-TLB1 handling code and slightly
      different TLB modification.
      This patch adds support for the FSL style MMU.
      Signed-off-by: default avatarAlexander Graf <agraf@suse.de>
    • Alexander Graf's avatar
      PPC: Add another 64 bits to instruction feature mask · a5858d7a
      Alexander Graf authored
      To enable quick runtime detection of instruction groups to the currently
      selected CPU emulation, we have a feature mask of what exactly the respective
      instruction supports.
      This feature mask is 64 bits long and we just successfully exceeded those 64
      bits. To add more features, we need to think of something.
      The easiest solution that came to my mind was to simply add another 64 bits
      that we can also match on. Since the comparison is only done on start of the
      qemu process to generate an internal opcode calling table, we should be fine
      on any performance penalties here.
      Signed-off-by: default avatarAlexander Graf <agraf@suse.de>
  17. 09 May, 2011 1 commit
  18. 20 Apr, 2011 1 commit
    • Stefan Weil's avatar
      Remove unused function parameters from gen_pc_load and rename the function · e87b7cb0
      Stefan Weil authored
      Function gen_pc_load was introduced in commit
      The only reason for parameter searched_pc was
      a debug statement in target-i386/translate.c.
      Parameter puc was needed by target-sparc until
      commit d7da2a10
      Remove searched_pc from the debug statement and remove both
      parameters from the parameter list of gen_pc_load.
      As the function name gen_pc_load was also misleading,
      it is now called restore_state_to_opc. This new name
      was suggested by Peter Maydell, thanks.
      v2: Remove last parameter, too, and rename the function.
      v3: Fix [] typo in target-arm/translate.c.
          Fix wrong SHA1 object name in commit message (copy+paste error).
      Cc: Aurelien Jarno <aurelien@aurel32.net>
      Reviewed-by: default avatarPeter Maydell <peter.maydell@linaro.org>
      Signed-off-by: default avatarStefan Weil <weil@mail.berlios.de>
  19. 09 Apr, 2011 1 commit
  20. 01 Apr, 2011 4 commits
    • David Gibson's avatar
      Parse SDR1 on mtspr instead of at translate time · bb593904
      David Gibson authored
      On ppc machines with hash table MMUs, the special purpose register SDR1
      contains both the base address of the encoded size (hashed) page tables.
      At present, we interpret the SDR1 value within the address translation
      path.  But because the encodings of the size for 32-bit and 64-bit are
      different this makes for a confusing branch on the MMU type with a bunch
      of curly shifts and masks in the middle of the translate path.
      This patch cleans things up by moving the interpretation on SDR1 into the
      helper function handling the write to the register.  This leaves a simple
      pre-sanitized base address and mask for the hash table in the CPUState
      structure which is easier to work with in the translation path.
      This makes the translation path more readable.  It addresses the FIXME
      comment currently in the mtsdr1 helper, by validating the SDR1 value during
      interpretation.  Finally it opens the way for emulating a pSeries-style
      partition where the hash table used for translation is not mapped into
      the guests's RAM.
      Signed-off-by: default avatarDavid Gibson <dwg@au1.ibm.com>
      Signed-off-by: default avatarAlexander Graf <agraf@suse.de>
    • David Gibson's avatar
      Correct ppc popcntb logic, implement popcntw and popcntd · eaabeef2
      David Gibson authored
      qemu already includes support for the popcntb instruction introduced
      in POWER5 (although it doesn't actually allow you to choose POWER5).
      However, the logic is slightly incorrect: it will generate results
      truncated to 32-bits when the CPU is in 32-bit mode.  This is not
      normal for powerpc - generally arithmetic instructions on a 64-bit
      powerpc cpu will generate full 64 bit results, it's just that only the
      low 32 bits will be significant for condition codes.
      This patch corrects this nit, which actually simplifies the code slightly.
      In addition, this patch implements the popcntw and popcntd
      instructions added in POWER7, in preparation for allowing POWER7 as an
      emulated CPU.
      Signed-off-by: default avatarDavid Gibson <dwg@au1.ibm.com>
      Signed-off-by: default avatarAlexander Graf <agraf@suse.de>
    • David Gibson's avatar
      Implement PowerPC slbmfee and slbmfev instructions · efdef95f
      David Gibson authored
      For a 64-bit PowerPC target, qemu correctly implements translation
      through the segment lookaside buffer.  Likewise it supports the
      slbmte instruction which is used to load entries into the SLB.
      However, it does not emulate the slbmfee and slbmfev instructions
      which read SLB entries back into registers.  Because these are
      only occasionally used in guests (mostly for debugging) we get
      away with it.
      However, given the recent SLB cleanups, it becomes quite easy to
      implement these, and thereby allow, amongst other things, a guest
      Linux to use xmon's command to dump the SLB.
      Signed-off-by: default avatarDavid Gibson <dwg@au1.ibm.com>
      Signed-off-by: default avatarAlexander Graf <agraf@suse.de>
    • Aurelien Jarno's avatar
      target-ppc: ext32u instead of andi with constant · 17d9b3af
      Aurelien Jarno authored
      Cc: Alexander Graf <agraf@suse.de>
      Signed-off-by: default avatarAurelien Jarno <aurelien@aurel32.net>
      Signed-off-by: default avatarAlexander Graf <agraf@suse.de>
  21. 22 Mar, 2011 1 commit
  22. 21 Jan, 2011 1 commit
  23. 31 Dec, 2010 1 commit