1. 24 Jan, 2011 2 commits
  2. 19 Dec, 2010 1 commit
  3. 04 Dec, 2010 1 commit
  4. 03 Dec, 2010 1 commit
  5. 03 Jul, 2010 2 commits
  6. 22 May, 2010 2 commits
  7. 16 May, 2010 1 commit
  8. 09 May, 2010 1 commit
  9. 06 May, 2010 2 commits
  10. 17 Apr, 2010 1 commit
  11. 12 Mar, 2010 2 commits
  12. 27 Jan, 2010 2 commits
  13. 08 Jan, 2010 3 commits
  14. 05 Dec, 2009 1 commit
  15. 01 Oct, 2009 2 commits
  16. 24 Aug, 2009 1 commit
    • Nathan Froyd's avatar
      cleanup cpu-exec.c, part 0/N: consolidate handle_cpu_signal · 0b5c1ce8
      Nathan Froyd authored
      
      
      handle_cpu_signal is very nearly copy-paste code for each target, with a
      few minor variations.  This patch sets up appropriate defaults for a
      generic handle_cpu_signal and provides overrides for particular targets
      that did things differently.  Fixing things like the persistent (XXX:
      use sigsetjmp) should now become somewhat easier.
      
      Previous comments on this patch suggest that the "activate soft MMU for
      this block" comments refer to defunct functionality.  I have removed
      such blocks for the appropriate targets in this patch.
      
      Signed-off-by: default avatarNathan Froyd <froydnj@codesourcery.com>
      Signed-off-by: default avatarAnthony Liguori <aliguori@us.ibm.com>
      0b5c1ce8
  17. 22 Aug, 2009 1 commit
  18. 04 Aug, 2009 1 commit
    • Igor Kovalenko's avatar
      Sparc64: replace tsptr with helper routine · 8194f35a
      Igor Kovalenko authored
      
      
      tl and tsptr of members sparc64 cpu state must be changed
      simultaneously to keep trap state window in sync with current
      trap level. Currently translation of store to tl does not change
      tsptr, which leads to corrupt trap state on corresponding
      trap level.
      
      This patch removes tsptr from sparc64 cpu state and replaces
      all uses with call to helper routine.
      
      Changes v0->v1:
      - reimplemented helper routine with tcg generator
      - on cpu reset trap type and pstate are populated with power-on reset
      values, including tl=maxtl
      
      Signed-off-by: default avatar <igor.v.kovalenko@gmail.com>
      Signed-off-by: default avatarBlue Swirl <blauwirbel@gmail.com>
      8194f35a
  19. 26 Jul, 2009 2 commits
    • Igor Kovalenko's avatar
      sparc64 really implement itlb/dtlb automatic replacement writes · f707726e
      Igor Kovalenko authored
      
      
      - implement "used" bit in tlb translation entry
      - mark tlb entry used if qemu code/data translation succeeds
      - fold i/d mmu replacement writes code into replace_tlb_1bit_lru which
      adds 1bit lru replacement algorithm; previously code tried to replace
      first unlocked entry only
      
      - extract more bitmasks to named macros
      - add "immu" or "dmmu" type name to debugging output where appropriate
      
      Signed-off-by: default avatar <igor.v.kovalenko@gmail.com>
      
      --
      Kind regards,
      Igor V. Kovalenko
      f707726e
    • Igor Kovalenko's avatar
      sparc64 name mmu registers and general cleanup · 6e8e7d4c
      Igor Kovalenko authored
      
      
      - add names to mmu registers, this helps understanding the code which
      uses/modifies them.
      - fold i/d mmu tlb entries tag and tte arrays into arrays of tlb entries
      - extract demap_tlb routine (code duplication)
      - extract replace_tlb routine (code duplication)
      
      - flush qemu tlb translations when replacing sparc64 mmu tlb entries
      
      I have no test case which demands flushing qemu translations,
      and this patch should have no other visible changes to runtime.
      
      Signed-off-by: default avatar <igor.v.kovalenko@gmail.com>
      
      --
      Kind regards,
      Igor V. Kovalenko
      6e8e7d4c
  20. 12 Jul, 2009 1 commit
    • Igor Kovalenko's avatar
      sparc64: trap handling corrections · 5210977a
      Igor Kovalenko authored
      On Sun, Jul 12, 2009 at 12:09 PM, Blue Swirl<blauwirbel@gmail.com> wrote:
      > On 7/12/09, Igor Kovalenko <igor.v.kovalenko@gmail.com> wrote:
      >> Good trap handling is required to process interrupts.
      >>  This patch fixes the following:
      >>
      >>  - sparc64 has no wim register
      >>  - sparc64 has no psret register, use IE bit of pstate
      >>   extract IE checking code to cpu_interrupts_enabled
      >>  - alternate globals are not available if cpu has GL feature
      >>   in this case bit AG of pstate is constant zero
      >>  - write to pstate must actually write pstate
      >>   even if cpu has GL feature
      >>
      >>  Also timer interrupt is handled using do_interrupt.
      >
      > A bit too much for one patch. Please also remove the code instead of
      > commenting out.
      
      I now excluded timer interrupt related part.
      To my mind other changes are essentially tied together.
      
      > PUT_PSR for Sparc64 needs CC_OP = CC_OP_FLAGS; like Sparc32.
      
      Fixed, please find attached the updated version.
      
      --
      Kind regards,
      Igor V. Kovalenko
      5210977a
  21. 19 May, 2009 1 commit
    • Paul Brook's avatar
      Hardware convenience library · 1ad2134f
      Paul Brook authored
      
      
      The only target dependency for most hardware is sizeof(target_phys_addr_t).
      Build these files into a convenience library, and use that instead of
      building for every target.
      
      Remove and poison various target specific macros to avoid bogus target
      dependencies creeping back in.
      
      Big/Little endian is not handled because devices should not know or care
      about this to start with.
      
      Signed-off-by: default avatarPaul Brook <paul@codesourcery.com>
      1ad2134f
  22. 10 May, 2009 1 commit
  23. 07 Mar, 2009 1 commit
  24. 23 Dec, 2008 3 commits
  25. 18 Nov, 2008 2 commits
  26. 06 Oct, 2008 1 commit
  27. 03 Oct, 2008 1 commit