1. 28 Aug, 2012 1 commit
    • Aurelien Jarno's avatar
      tcg/mips: fix broken CONFIG_TCG_PASS_AREG0 code · 18fec301
      Aurelien Jarno authored
      The CONFIG_TCG_PASS_AREG0 code for calling ld/st helpers was
      broken in that it did not respect the ABI requirement that 64
      bit values were passed in even-odd register pairs. The simplest
      way to fix this is to implement some new utility functions
      for marshalling function arguments into the correct registers
      and stack, so that the code which sets up the address and
      data arguments does not need to care whether there has been
      a preceding env argument.
      
      Based on commit 9716ef3b
      
       for ARM by Peter Maydell.
      Signed-off-by: default avatarAurelien Jarno <aurelien@aurel32.net>
      Reviewed-by: default avatarPeter Maydell <peter.maydell@linaro.org>
      18fec301
  2. 18 Mar, 2012 1 commit
  3. 14 Mar, 2012 1 commit
    • Andreas Färber's avatar
      Rename CPUState -> CPUArchState · 9349b4f9
      Andreas Färber authored
      
      
      Scripted conversion:
        for file in *.[hc] hw/*.[hc] hw/kvm/*.[hc] linux-user/*.[hc] linux-user/m68k/*.[hc] bsd-user/*.[hc] darwin-user/*.[hc] tcg/*/*.[hc] target-*/cpu.h; do
          sed -i "s/CPUState/CPUArchState/g" $file
        done
      
      All occurrences of CPUArchState are expected to be replaced by QOM CPUState,
      once all targets are QOM'ified and common fields have been extracted.
      Signed-off-by: default avatarAndreas Färber <afaerber@suse.de>
      Reviewed-by: default avatarAnthony Liguori <aliguori@us.ibm.com>
      9349b4f9
  4. 14 Nov, 2011 1 commit
  5. 20 Jul, 2011 1 commit
  6. 26 Jun, 2011 2 commits
  7. 11 Jan, 2011 1 commit
  8. 08 Jan, 2011 1 commit
  9. 09 Jun, 2010 2 commits
  10. 13 Apr, 2010 1 commit
    • Stefan Weil's avatar
      tcp/mips: Change TCG_AREG0 (fp -> s0) · 60bf84cf
      Stefan Weil authored
      
      
      Register fp (frame pointer) is a bad choice for compilations
      without optimisation, because the compiler makes heavy use
      of this register (so the resulting code crashes).
      
      Register s0 had been used for TCG_AREG1 in earlier releases,
      but was no longer used and is now free for TCG_AREG0.
      
      The resulting code works for compilations without
      optimisation (tested with qemu mips in qemu mips
      on x86 host).
      Signed-off-by: default avatarStefan Weil <weil@mail.berlios.de>
      Signed-off-by: default avatarAurelien Jarno <aurelien@aurel32.net>
      60bf84cf
  11. 05 Apr, 2010 2 commits
  12. 04 Apr, 2010 1 commit
    • Paul Brook's avatar
      Split TLB addend and target_phys_addr_t · 355b1943
      Paul Brook authored
      
      
      Historically the qemu tlb "addend" field was used for both RAM and IO accesses,
      so needed to be able to hold both host addresses (unsigned long) and guest
      physical addresses (target_phys_addr_t).  However since the introduction of
      the iotlb field it has only been used for RAM accesses.
      
      This means we can change the type of addend to unsigned long, and remove
      associated hacks in the big-endian TCG backends.
      
      We can also remove the host dependence from target_phys_addr_t.
      Signed-off-by: default avatarPaul Brook <paul@codesourcery.com>
      355b1943
  13. 28 Mar, 2010 1 commit
  14. 27 Mar, 2010 3 commits
  15. 26 Mar, 2010 3 commits
  16. 09 Feb, 2010 1 commit
  17. 08 Feb, 2010 2 commits
  18. 30 Nov, 2009 1 commit
    • Aurelien Jarno's avatar
      tcg: initial mips support · afa05235
      Aurelien Jarno authored
      
      
      Based on a patch from Arnaud Patard (Rtp) <arnaud.patard@rtp-net.org>
      
      A few words about design choices:
      * Two registers, at and t0, are reserved for TCG internal use. They are
        useful for bswap and 64-bit ops.
      * Most ops supports a constant argument with value 0, which is actually
        mapped to the zero register.
      * While the at register is available for constant loading, ops only
        support a limited range of constants. TCG does a better job doing the
        register allocation and constant loading by itself. There are plenty of
        registers available anyway.
      Signed-off-by: default avatarAurelien Jarno <aurelien@aurel32.net>
      afa05235