1. 01 May, 2012 1 commit
  2. 21 Apr, 2012 1 commit
  3. 14 Apr, 2012 2 commits
  4. 07 Apr, 2012 3 commits
  5. 18 Mar, 2012 1 commit
  6. 14 Mar, 2012 1 commit
    • Andreas Färber's avatar
      Rename CPUState -> CPUArchState · 9349b4f9
      Andreas Färber authored
      Scripted conversion:
        for file in *.[hc] hw/*.[hc] hw/kvm/*.[hc] linux-user/*.[hc] linux-user/m68k/*.[hc] bsd-user/*.[hc] darwin-user/*.[hc] tcg/*/*.[hc] target-*/cpu.h; do
          sed -i "s/CPUState/CPUArchState/g" $file
        done
      
      All occurrences of CPUArchState are expected to be replaced by QOM CPUState,
      once all targets are QOM'ified and common fields have been extracted.
      Signed-off-by: default avatarAndreas Färber <afaerber@suse.de>
      Reviewed-by: default avatarAnthony Liguori <aliguori@us.ibm.com>
      9349b4f9
  7. 08 Mar, 2012 3 commits
  8. 04 Jan, 2012 4 commits
  9. 31 Oct, 2011 1 commit
    • Stefan Weil's avatar
      tcg: Add bytecode generator for tcg interpreter · 7316329a
      Stefan Weil authored
      Unlike other tcg target code generators, this one does not generate
      machine code for some cpu. It generates machine independent bytecode
      which is interpreted later.
      
      This allows running QEMU on any host.
      
      Interpreted bytecode is slower than direct execution of generated
      machine code.
      Signed-off-by: default avatarStefan Weil <sw@weilnetz.de>
      7316329a
  10. 30 Oct, 2011 1 commit
  11. 21 Oct, 2011 1 commit
  12. 01 Oct, 2011 2 commits
  13. 20 Jul, 2011 1 commit
  14. 12 Jul, 2011 1 commit
    • Peter Maydell's avatar
      exec-all.h: Make MAX_OP_PER_INSTR large enough for target-arm's uses · 5b620fb6
      Peter Maydell authored
      The target-arm frontend's worst-case TCG ops per instr is 194 (and in
      general many of the "load multiple registers" ARM instructions generate
      more than 100 TCG ops). Raise MAX_OP_PER_INSTR accordingly to avoid
      possible buffer overruns.
      
      Since it doesn't make any sense for the "64 bit guest on 32 bit host"
      case to have a smaller limit than the normal case, we collapse the
      two cases back into each other again.
      
      (This increase costs us about 14K in extra static buffer space and
      21K of extra margin at the end of a 32MB codegen buffer.)
      Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
      Signed-off-by: default avatarBlue Swirl <blauwirbel@gmail.com>
      5b620fb6
  15. 26 Jun, 2011 2 commits
  16. 31 May, 2011 1 commit
  17. 22 May, 2011 1 commit
  18. 20 May, 2011 1 commit
  19. 20 Apr, 2011 2 commits
  20. 10 Feb, 2011 1 commit
  21. 23 Jan, 2011 1 commit
  22. 31 Dec, 2010 1 commit
    • Aurelien Jarno's avatar
      TCG: Improve tb_phys_hash_func() · f96a3834
      Aurelien Jarno authored
      Most of emulated CPU have instructions aligned on 16 or 32 bits, while
      on others GCC tries to align the target jump location. This means that
      1/2 or 3/4 of tb_phys_hash entries are never used.
      
      Update the hash function tb_phys_hash_func() to ignore the two lowest
      bits of the address. This brings a 6% speed-up when booting a MIPS
      image.
      Signed-off-by: default avatarAurelien Jarno <aurelien@aurel32.net>
      f96a3834
  23. 21 Dec, 2010 1 commit
    • Aurelien Jarno's avatar
      tcg-arm: fix __clear_cache() warning · 4a1e19ae
      Aurelien Jarno authored
      Use __builtin___clear_cache() instead of __clear_cache() to avoid having
      to define the function as extern. Fix the following warning:
      
      | In file included from qemu/cpus.c:34:
      | qemu/exec-all.h: In function 'tb_set_jmp_target1':
      | qemu/exec-all.h:208: error: nested extern declaration of '__clear_cache'
      | make[1]: *** [cpus.o] Error 1
      | make: *** [subdir-i386-softmmu] Error 2
      Signed-off-by: default avatarAurelien Jarno <aurelien@aurel32.net>
      4a1e19ae
  24. 20 Oct, 2010 1 commit
  25. 24 Jul, 2010 1 commit
  26. 21 Jul, 2010 1 commit
  27. 09 Jun, 2010 1 commit
  28. 11 May, 2010 1 commit
  29. 01 May, 2010 1 commit
    • Stuart Brady's avatar
      Clean up definition of MAX_OPC_PARAM · 4d0e4ac7
      Stuart Brady authored
      MAX_OPC_PARAM is intended to refer to the maximum number of entries used
      in gen_opparam_buf[] for any single helper call.  It is currently defined
      as 10, but for 32-bit archs, the correct value (with a maximum for four
      helper arguments) is 14, and for 64-bit archs, only 9 entries are needed.
      
      tcg_gen_callN() fills four entries with the function address, flags,
      number of args, etc. and on 32-bit archs uses a further two entries per
      argument (with a maximum of four helper arguments), plus two more for the
      return value.  On 64-bit archs, only half as many entries are used for the
      args and the return value.
      
      In reality, TBs tend not to consist purely of helper calls exceeding the
      stated 10 gen_opparam_buf[] entries, so this would never actually be a
      problem on 32-bit archs, but the definition is still rather confusing.
      Signed-off-by: default avatarStuart Brady <sdb@zubnet.me.uk>
      Signed-off-by: default avatarBlue Swirl <blauwirbel@gmail.com>
      4d0e4ac7