Commit ead9360e authored by ths's avatar ths
Browse files

Partial support for 34K multithreading, not functional yet.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3156 c046a42c-6fe2-441c-8c8c-71466251a162
parent 606b41e7
......@@ -194,7 +194,7 @@ static inline TranslationBlock *tb_find_fast(void)
#elif defined(TARGET_MIPS)
flags = env->hflags & (MIPS_HFLAG_TMASK | MIPS_HFLAG_BMASK);
cs_base = 0;
pc = env->PC;
pc = env->PC[env->current_tc];
#elif defined(TARGET_M68K)
flags = (env->fpcr & M68K_FPCR_PREC) /* Bit 6 */
| (env->sr & SR_S) /* Bit 13 */
......
......@@ -559,17 +559,17 @@ static int cpu_gdb_read_registers(CPUState *env, uint8_t *mem_buf)
ptr = mem_buf;
for (i = 0; i < 32; i++)
{
*(target_ulong *)ptr = tswapl(env->gpr[i]);
*(target_ulong *)ptr = tswapl(env->gpr[i][env->current_tc]);
ptr += sizeof(target_ulong);
}
*(target_ulong *)ptr = tswapl(env->CP0_Status);
ptr += sizeof(target_ulong);
*(target_ulong *)ptr = tswapl(env->LO);
*(target_ulong *)ptr = tswapl(env->LO[0][env->current_tc]);
ptr += sizeof(target_ulong);
*(target_ulong *)ptr = tswapl(env->HI);
*(target_ulong *)ptr = tswapl(env->HI[0][env->current_tc]);
ptr += sizeof(target_ulong);
*(target_ulong *)ptr = tswapl(env->CP0_BadVAddr);
......@@ -578,21 +578,21 @@ static int cpu_gdb_read_registers(CPUState *env, uint8_t *mem_buf)
*(target_ulong *)ptr = tswapl(env->CP0_Cause);
ptr += sizeof(target_ulong);
*(target_ulong *)ptr = tswapl(env->PC);
*(target_ulong *)ptr = tswapl(env->PC[env->current_tc]);
ptr += sizeof(target_ulong);
if (env->CP0_Config1 & (1 << CP0C1_FP))
{
for (i = 0; i < 32; i++)
{
*(target_ulong *)ptr = tswapl(env->fpr[i].fs[FP_ENDIAN_IDX]);
*(target_ulong *)ptr = tswapl(env->fpu->fpr[i].fs[FP_ENDIAN_IDX]);
ptr += sizeof(target_ulong);
}
*(target_ulong *)ptr = tswapl(env->fcr31);
*(target_ulong *)ptr = tswapl(env->fpu->fcr31);
ptr += sizeof(target_ulong);
*(target_ulong *)ptr = tswapl(env->fcr0);
*(target_ulong *)ptr = tswapl(env->fpu->fcr0);
ptr += sizeof(target_ulong);
}
......@@ -611,7 +611,7 @@ static unsigned int ieee_rm[] =
float_round_down
};
#define RESTORE_ROUNDING_MODE \
set_float_rounding_mode(ieee_rm[env->fcr31 & 3], &env->fp_status)
set_float_rounding_mode(ieee_rm[env->fpu->fcr31 & 3], &env->fpu->fp_status)
static void cpu_gdb_write_registers(CPUState *env, uint8_t *mem_buf, int size)
{
......@@ -621,17 +621,17 @@ static void cpu_gdb_write_registers(CPUState *env, uint8_t *mem_buf, int size)
ptr = mem_buf;
for (i = 0; i < 32; i++)
{
env->gpr[i] = tswapl(*(target_ulong *)ptr);
env->gpr[i][env->current_tc] = tswapl(*(target_ulong *)ptr);
ptr += sizeof(target_ulong);
}
env->CP0_Status = tswapl(*(target_ulong *)ptr);
ptr += sizeof(target_ulong);
env->LO = tswapl(*(target_ulong *)ptr);
env->LO[0][env->current_tc] = tswapl(*(target_ulong *)ptr);
ptr += sizeof(target_ulong);
env->HI = tswapl(*(target_ulong *)ptr);
env->HI[0][env->current_tc] = tswapl(*(target_ulong *)ptr);
ptr += sizeof(target_ulong);
env->CP0_BadVAddr = tswapl(*(target_ulong *)ptr);
......@@ -640,21 +640,21 @@ static void cpu_gdb_write_registers(CPUState *env, uint8_t *mem_buf, int size)
env->CP0_Cause = tswapl(*(target_ulong *)ptr);
ptr += sizeof(target_ulong);
env->PC = tswapl(*(target_ulong *)ptr);
env->PC[env->current_tc] = tswapl(*(target_ulong *)ptr);
ptr += sizeof(target_ulong);
if (env->CP0_Config1 & (1 << CP0C1_FP))
{
for (i = 0; i < 32; i++)
{
env->fpr[i].fs[FP_ENDIAN_IDX] = tswapl(*(target_ulong *)ptr);
env->fpu->fpr[i].fs[FP_ENDIAN_IDX] = tswapl(*(target_ulong *)ptr);
ptr += sizeof(target_ulong);
}
env->fcr31 = tswapl(*(target_ulong *)ptr) & 0x0183FFFF;
env->fpu->fcr31 = tswapl(*(target_ulong *)ptr) & 0x0183FFFF;
ptr += sizeof(target_ulong);
env->fcr0 = tswapl(*(target_ulong *)ptr);
env->fpu->fcr0 = tswapl(*(target_ulong *)ptr);
ptr += sizeof(target_ulong);
/* set rounding mode */
......@@ -775,7 +775,7 @@ static int gdb_handle_packet(GDBState *s, CPUState *env, const char *line_buf)
#elif defined (TARGET_SH4)
env->pc = addr;
#elif defined (TARGET_MIPS)
env->PC = addr;
env->PC[env->current_tc] = addr;
#endif
}
#ifdef CONFIG_USER_ONLY
......@@ -799,7 +799,7 @@ static int gdb_handle_packet(GDBState *s, CPUState *env, const char *line_buf)
#elif defined (TARGET_SH4)
env->pc = addr;
#elif defined (TARGET_MIPS)
env->PC = addr;
env->PC[env->current_tc] = addr;
#endif
}
cpu_single_step(env, 1);
......
......@@ -77,7 +77,7 @@ void load_kernel (CPUState *env, int ram_size, const char *kernel_filename,
if (kernel_size >= 0) {
if ((entry & ~0x7fffffffULL) == 0x80000000)
entry = (int32_t)entry;
env->PC = entry;
env->PC[env->current_tc] = entry;
} else {
fprintf(stderr, "qemu: could not load kernel '%s'\n",
kernel_filename);
......
......@@ -10,7 +10,7 @@ uint32_t cpu_mips_get_random (CPUState *env)
static uint32_t seed = 0;
uint32_t idx;
seed = seed * 314159 + 1;
idx = (seed >> 16) % (env->nb_tlb - env->CP0_Wired) + env->CP0_Wired;
idx = (seed >> 16) % (env->tlb->nb_tlb - env->CP0_Wired) + env->CP0_Wired;
return idx;
}
......
......@@ -1374,8 +1374,8 @@ void cpu_loop(CPUMIPSState *env)
trapnr = cpu_mips_exec(env);
switch(trapnr) {
case EXCP_SYSCALL:
syscall_num = env->gpr[2] - 4000;
env->PC += 4;
syscall_num = env->gpr[2][env->current_tc] - 4000;
env->PC[env->current_tc] += 4;
if (syscall_num >= sizeof(mips_syscall_args)) {
ret = -ENOSYS;
} else {
......@@ -1384,7 +1384,7 @@ void cpu_loop(CPUMIPSState *env)
target_ulong arg5 = 0, arg6 = 0, arg7 = 0, arg8 = 0;
nb_args = mips_syscall_args[syscall_num];
sp_reg = env->gpr[29];
sp_reg = env->gpr[29][env->current_tc];
switch (nb_args) {
/* these arguments are taken from the stack */
case 8: arg8 = tgetl(sp_reg + 28);
......@@ -1394,18 +1394,20 @@ void cpu_loop(CPUMIPSState *env)
default:
break;
}
ret = do_syscall(env, env->gpr[2],
env->gpr[4], env->gpr[5],
env->gpr[6], env->gpr[7],
ret = do_syscall(env, env->gpr[2][env->current_tc],
env->gpr[4][env->current_tc],
env->gpr[5][env->current_tc],
env->gpr[6][env->current_tc],
env->gpr[7][env->current_tc],
arg5, arg6/*, arg7, arg8*/);
}
if ((unsigned int)ret >= (unsigned int)(-1133)) {
env->gpr[7] = 1; /* error flag */
env->gpr[7][env->current_tc] = 1; /* error flag */
ret = -ret;
} else {
env->gpr[7] = 0; /* error flag */
env->gpr[7][env->current_tc] = 0; /* error flag */
}
env->gpr[2] = ret;
env->gpr[2][env->current_tc] = ret;
break;
case EXCP_TLBL:
case EXCP_TLBS:
......@@ -2053,9 +2055,9 @@ int main(int argc, char **argv)
cpu_mips_register(env, def);
for(i = 0; i < 32; i++) {
env->gpr[i] = regs->regs[i];
env->gpr[i][env->current_tc] = regs->regs[i];
}
env->PC = regs->cp0_epc;
env->PC[env->current_tc] = regs->cp0_epc;
}
#elif defined(TARGET_SH4)
{
......
......@@ -1686,10 +1686,10 @@ setup_sigcontext(CPUState *regs, struct target_sigcontext *sc)
{
int err = 0;
err |= __put_user(regs->PC, &sc->sc_pc);
err |= __put_user(regs->PC[regs->current_tc], &sc->sc_pc);
#define save_gp_reg(i) do { \
err |= __put_user(regs->gpr[i], &sc->sc_regs[i]); \
#define save_gp_reg(i) do { \
err |= __put_user(regs->gpr[i][regs->current_tc], &sc->sc_regs[i]); \
} while(0)
__put_user(0, &sc->sc_regs[0]); save_gp_reg(1); save_gp_reg(2);
save_gp_reg(3); save_gp_reg(4); save_gp_reg(5); save_gp_reg(6);
......@@ -1702,8 +1702,8 @@ setup_sigcontext(CPUState *regs, struct target_sigcontext *sc)
save_gp_reg(31);
#undef save_gp_reg
err |= __put_user(regs->HI, &sc->sc_mdhi);
err |= __put_user(regs->LO, &sc->sc_mdlo);
err |= __put_user(regs->HI[0][regs->current_tc], &sc->sc_mdhi);
err |= __put_user(regs->LO[0][regs->current_tc], &sc->sc_mdlo);
/* Not used yet, but might be useful if we ever have DSP suppport */
#if 0
......@@ -1763,11 +1763,11 @@ restore_sigcontext(CPUState *regs, struct target_sigcontext *sc)
err |= __get_user(regs->CP0_EPC, &sc->sc_pc);
err |= __get_user(regs->HI, &sc->sc_mdhi);
err |= __get_user(regs->LO, &sc->sc_mdlo);
err |= __get_user(regs->HI[0][regs->current_tc], &sc->sc_mdhi);
err |= __get_user(regs->LO[0][regs->current_tc], &sc->sc_mdlo);
#define restore_gp_reg(i) do { \
err |= __get_user(regs->gpr[i], &sc->sc_regs[i]); \
#define restore_gp_reg(i) do { \
err |= __get_user(regs->gpr[i][regs->current_tc], &sc->sc_regs[i]); \
} while(0)
restore_gp_reg( 1); restore_gp_reg( 2); restore_gp_reg( 3);
restore_gp_reg( 4); restore_gp_reg( 5); restore_gp_reg( 6);
......@@ -1833,7 +1833,7 @@ get_sigframe(struct emulated_sigaction *ka, CPUState *regs, size_t frame_size)
unsigned long sp;
/* Default to using normal stack */
sp = regs->gpr[29];
sp = regs->gpr[29][regs->current_tc];
/*
* FPU emulator may have it's own trampoline active just
......@@ -1881,15 +1881,15 @@ static void setup_frame(int sig, struct emulated_sigaction * ka,
* $25 and PC point to the signal handler, $29 points to the
* struct sigframe.
*/
regs->gpr[ 4] = sig;
regs->gpr[ 5] = 0;
regs->gpr[ 6] = h2g(&frame->sf_sc);
regs->gpr[29] = h2g(frame);
regs->gpr[31] = h2g(frame->sf_code);
regs->gpr[ 4][regs->current_tc] = sig;
regs->gpr[ 5][regs->current_tc] = 0;
regs->gpr[ 6][regs->current_tc] = h2g(&frame->sf_sc);
regs->gpr[29][regs->current_tc] = h2g(frame);
regs->gpr[31][regs->current_tc] = h2g(frame->sf_code);
/* The original kernel code sets CP0_EPC to the handler
* since it returns to userland using eret
* we cannot do this here, and we must set PC directly */
regs->PC = regs->gpr[25] = ka->sa._sa_handler;
regs->PC[regs->current_tc] = regs->gpr[25][regs->current_tc] = ka->sa._sa_handler;
return;
give_sigsegv:
......@@ -1907,7 +1907,7 @@ long do_sigreturn(CPUState *regs)
#if defined(DEBUG_SIGNAL)
fprintf(stderr, "do_sigreturn\n");
#endif
frame = (struct sigframe *) regs->gpr[29];
frame = (struct sigframe *) regs->gpr[29][regs->current_tc];
if (!access_ok(VERIFY_READ, frame, sizeof(*frame)))
goto badframe;
......@@ -1934,7 +1934,7 @@ long do_sigreturn(CPUState *regs)
/* Unreached */
#endif
regs->PC = regs->CP0_EPC;
regs->PC[regs->current_tc] = regs->CP0_EPC;
/* I am not sure this is right, but it seems to work
* maybe a problem with nested signals ? */
regs->CP0_EPC = 0;
......
......@@ -2189,8 +2189,8 @@ int do_fork(CPUState *env, unsigned int flags, unsigned long newsp)
/* ??? is this sufficient? */
#elif defined(TARGET_MIPS)
if (!newsp)
newsp = env->gpr[29];
new_env->gpr[29] = newsp;
newsp = env->gpr[29][env->current_tc];
new_env->gpr[29][env->current_tc] = newsp;
#elif defined(TARGET_PPC)
if (!newsp)
newsp = env->gpr[1];
......@@ -2777,7 +2777,8 @@ long do_syscall(void *cpu_env, int num, long arg1, long arg2, long arg3,
ret = get_errno(pipe(host_pipe));
if (!is_error(ret)) {
#if defined(TARGET_MIPS)
((CPUMIPSState*)cpu_env)->gpr[3] = host_pipe[1];
CPUMIPSState *env = (CPUMIPSState*)cpu_env;
env->gpr[3][env->current_tc] = host_pipe[1];
ret = host_pipe[0];
#else
tput32(arg1, host_pipe[0]);
......
......@@ -309,6 +309,10 @@ static void do_info_cpus(void)
term_printf(" pc=0x" TARGET_FMT_lx " npc=0x" TARGET_FMT_lx, env->pc, env->npc);
if (env->halted)
term_printf(" (halted)");
#elif defined(TARGET_MIPS)
term_printf(" PC=0x" TARGET_FMT_lx, env->PC[env->current_tc]);
if (env->halted)
term_printf(" (halted)");
#endif
term_printf("\n");
}
......
......@@ -17,21 +17,7 @@ typedef unsigned char uint_fast8_t;
typedef unsigned int uint_fast16_t;
#endif
typedef union fpr_t fpr_t;
union fpr_t {
float64 fd; /* ieee double precision */
float32 fs[2];/* ieee single precision */
uint64_t d; /* binary double fixed-point */
uint32_t w[2]; /* binary single fixed-point */
};
/* define FP_ENDIAN_IDX to access the same location
* in the fpr_t union regardless of the host endianess
*/
#if defined(WORDS_BIGENDIAN)
# define FP_ENDIAN_IDX 1
#else
# define FP_ENDIAN_IDX 0
#endif
struct CPUMIPSState;
typedef struct r4k_tlb_t r4k_tlb_t;
struct r4k_tlb_t {
......@@ -48,20 +34,40 @@ struct r4k_tlb_t {
target_ulong PFN[2];
};
typedef struct mips_def_t mips_def_t;
typedef struct CPUMIPSTLBContext CPUMIPSTLBContext;
struct CPUMIPSTLBContext {
uint32_t nb_tlb;
uint32_t tlb_in_use;
int (*map_address) (struct CPUMIPSState *env, target_ulong *physical, int *prot, target_ulong address, int rw, int access_type);
void (*do_tlbwi) (void);
void (*do_tlbwr) (void);
void (*do_tlbp) (void);
void (*do_tlbr) (void);
union {
struct {
r4k_tlb_t tlb[MIPS_TLB_MAX];
} r4k;
} mmu;
};
typedef struct CPUMIPSState CPUMIPSState;
struct CPUMIPSState {
/* General integer registers */
target_ulong gpr[32];
/* Special registers */
target_ulong PC;
#if TARGET_LONG_BITS > HOST_LONG_BITS
target_ulong t0;
target_ulong t1;
target_ulong t2;
typedef union fpr_t fpr_t;
union fpr_t {
float64 fd; /* ieee double precision */
float32 fs[2];/* ieee single precision */
uint64_t d; /* binary double fixed-point */
uint32_t w[2]; /* binary single fixed-point */
};
/* define FP_ENDIAN_IDX to access the same location
* in the fpr_t union regardless of the host endianess
*/
#if defined(WORDS_BIGENDIAN)
# define FP_ENDIAN_IDX 1
#else
# define FP_ENDIAN_IDX 0
#endif
target_ulong HI, LO;
typedef struct CPUMIPSFPUContext CPUMIPSFPUContext;
struct CPUMIPSFPUContext {
/* Floating point registers */
fpr_t fpr[32];
#ifndef USE_HOST_FLOAT_REGS
......@@ -99,30 +105,161 @@ struct CPUMIPSState {
#define FP_DIV0 8
#define FP_INVALID 16
#define FP_UNIMPLEMENTED 32
};
typedef struct CPUMIPSMVPContext CPUMIPSMVPContext;
struct CPUMIPSMVPContext {
int32_t CP0_MVPControl;
#define CP0MVPCo_CPA 3
#define CP0MVPCo_STLB 2
#define CP0MVPCo_VPC 1
#define CP0MVPCo_EVP 0
int32_t CP0_MVPConf0;
#define CP0MVPC0_M 31
#define CP0MVPC0_TLBS 29
#define CP0MVPC0_GS 28
#define CP0MVPC0_PCP 27
#define CP0MVPC0_PTLBE 16
#define CP0MVPC0_TCA 15
#define CP0MVPC0_PVPE 10
#define CP0MVPC0_PTC 0
int32_t CP0_MVPConf1;
#define CP0MVPC1_CIM 31
#define CP0MVPC1_CIF 30
#define CP0MVPC1_PCX 20
#define CP0MVPC1_PCP2 10
#define CP0MVPC1_PCP1 0
};
typedef struct mips_def_t mips_def_t;
#define MIPS_SHADOW_SET_MAX 16
#define MIPS_TC_MAX 5
#define MIPS_DSP_ACC 4
typedef struct CPUMIPSState CPUMIPSState;
struct CPUMIPSState {
/* General integer registers */
target_ulong gpr[32][MIPS_SHADOW_SET_MAX];
/* Special registers */
target_ulong PC[MIPS_TC_MAX];
#if TARGET_LONG_BITS > HOST_LONG_BITS
target_ulong t0;
target_ulong t1;
target_ulong t2;
#endif
target_ulong HI[MIPS_DSP_ACC][MIPS_TC_MAX];
target_ulong LO[MIPS_DSP_ACC][MIPS_TC_MAX];
target_ulong ACX[MIPS_DSP_ACC][MIPS_TC_MAX];
target_ulong DSPControl[MIPS_TC_MAX];
CPUMIPSMVPContext *mvp;
CPUMIPSTLBContext *tlb;
CPUMIPSFPUContext *fpu;
uint32_t current_tc;
uint32_t nb_tlb;
uint32_t tlb_in_use;
uint32_t SEGBITS;
target_ulong SEGMask;
int (*map_address) (CPUMIPSState *env, target_ulong *physical, int *prot, target_ulong address, int rw, int access_type);
void (*do_tlbwi) (void);
void (*do_tlbwr) (void);
void (*do_tlbp) (void);
void (*do_tlbr) (void);
union {
struct {
r4k_tlb_t tlb[MIPS_TLB_MAX];
} r4k;
} mmu;
int32_t CP0_Index;
/* CP0_MVP* are per MVP registers. */
int32_t CP0_Random;
int32_t CP0_VPEControl;
#define CP0VPECo_YSI 21
#define CP0VPECo_GSI 20
#define CP0VPECo_EXCPT 16
#define CP0VPECo_TE 15
#define CP0VPECo_TargTC 0
int32_t CP0_VPEConf0;
#define CP0VPEC0_M 31
#define CP0VPEC0_XTC 21
#define CP0VPEC0_TCS 19
#define CP0VPEC0_SCS 18
#define CP0VPEC0_DSC 17
#define CP0VPEC0_ICS 16
#define CP0VPEC0_MVP 1
#define CP0VPEC0_VPA 0
int32_t CP0_VPEConf1;
#define CP0VPEC1_NCX 20
#define CP0VPEC1_NCP2 10
#define CP0VPEC1_NCP1 0
target_ulong CP0_YQMask;
target_ulong CP0_VPESchedule;
target_ulong CP0_VPEScheFBack;
int32_t CP0_VPEOpt;
#define CP0VPEOpt_IWX7 15
#define CP0VPEOpt_IWX6 14
#define CP0VPEOpt_IWX5 13
#define CP0VPEOpt_IWX4 12
#define CP0VPEOpt_IWX3 11
#define CP0VPEOpt_IWX2 10
#define CP0VPEOpt_IWX1 9
#define CP0VPEOpt_IWX0 8
#define CP0VPEOpt_DWX7 7
#define CP0VPEOpt_DWX6 6
#define CP0VPEOpt_DWX5 5
#define CP0VPEOpt_DWX4 4
#define CP0VPEOpt_DWX3 3
#define CP0VPEOpt_DWX2 2
#define CP0VPEOpt_DWX1 1
#define CP0VPEOpt_DWX0 0
target_ulong CP0_EntryLo0;
int32_t CP0_TCStatus[MIPS_TC_MAX];
#define CP0TCSt_TCU3 31
#define CP0TCSt_TCU2 30
#define CP0TCSt_TCU1 29
#define CP0TCSt_TCU0 28
#define CP0TCSt_TMX 27
#define CP0TCSt_RNST 23
#define CP0TCSt_TDS 21
#define CP0TCSt_DT 20
#define CP0TCSt_DA 15
#define CP0TCSt_A 13
#define CP0TCSt_TKSU 11
#define CP0TCSt_IXMT 10
#define CP0TCSt_TASID 0
int32_t CP0_TCBind[MIPS_TC_MAX];
#define CP0TCBd_CurTC 21
#define CP0TCBd_TBE 17
#define CP0TCBd_CurVPE 0
target_ulong CP0_TCHalt[MIPS_TC_MAX];
target_ulong CP0_TCContext[MIPS_TC_MAX];
target_ulong CP0_TCSchedule[MIPS_TC_MAX];
target_ulong CP0_TCScheFBack[MIPS_TC_MAX];
target_ulong CP0_EntryLo1;
target_ulong CP0_Context;
int32_t CP0_PageMask;
int32_t CP0_PageGrain;
int32_t CP0_Wired;
int32_t CP0_SRSConf0_rw_bitmask;
int32_t CP0_SRSConf0;
#define CP0SRSC0_M 31
#define CP0SRSC0_SRS3 20
#define CP0SRSC0_SRS2 10
#define CP0SRSC0_SRS1 0
int32_t CP0_SRSConf1_rw_bitmask;
int32_t CP0_SRSConf1;
#define CP0SRSC1_M 31
#define CP0SRSC1_SRS6 20
#define CP0SRSC1_SRS5 10
#define CP0SRSC1_SRS4 0
int32_t CP0_SRSConf2_rw_bitmask;
int32_t CP0_SRSConf2;
#define CP0SRSC2_M 31
#define CP0SRSC2_SRS9 20
#define CP0SRSC2_SRS8 10
#define CP0SRSC2_SRS7 0
int32_t CP0_SRSConf3_rw_bitmask;
int32_t CP0_SRSConf3;
#define CP0SRSC3_M 31
#define CP0SRSC3_SRS12 20
#define CP0SRSC3_SRS11 10
#define CP0SRSC3_SRS10 0
int32_t CP0_SRSConf4_rw_bitmask;
int32_t CP0_SRSConf4;
#define CP0SRSC4_SRS15 20
#define CP0SRSC4_SRS14 10
#define CP0SRSC4_SRS13 0
int32_t CP0_HWREna;
target_ulong CP0_BadVAddr;
int32_t CP0_Count;
......@@ -152,8 +289,24 @@ struct CPUMIPSState {
#define CP0St_EXL 1
#define CP0St_IE 0
int32_t CP0_IntCtl;
#define CP0IntCtl_IPTI 29
#define CP0IntCtl_IPPC1 26
#define CP0IntCtl_VS 5
int32_t CP0_SRSCtl;
#define CP0SRSCtl_HSS 26
#define CP0SRSCtl_EICSS 18
#define CP0SRSCtl_ESS 12
#define CP0SRSCtl_PSS 6
#define CP0SRSCtl_CSS 0
int32_t CP0_SRSMap;
#define CP0SRSMap_SSV7 28
#define CP0SRSMap_SSV6 24
#define CP0SRSMap_SSV5 20
#define CP0SRSMap_SSV4 16
#define CP0SRSMap_SSV3 12
#define CP0SRSMap_SSV2 8
#define CP0SRSMap_SSV1 4
#define CP0SRSMap_SSV0 0
int32_t CP0_Cause;
#define CP0Ca_BD 31
#define CP0Ca_TI 30
......@@ -219,13 +372,14 @@ struct CPUMIPSState {
#define CP0C3_TL 0
int32_t CP0_Config6;
int32_t CP0_Config7;
/* XXX: Maybe make LLAddr per-TC? */
target_ulong CP0_LLAddr;
target_ulong CP0_WatchLo[8];
int32_t CP0_WatchHi[8];
target_ulong CP0_XContext;
int32_t CP0_Framemask;
int32_t CP0_Debug;
#define CPDB_DBD 31
#define CP0DB_DBD 31
#define CP0DB_DM 30
#define CP0DB_LSNM 28
#define CP0DB_Doze 27
......@@ -243,6 +397,7 @@ struct CPUMIPSState {