full system SPARC emulation (Blue Swirl)

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1083 c046a42c-6fe2-441c-8c8c-71466251a162

target-sparc/cpu.h

@@ -9,8 +9,10 @@
 
 /* trap definitions */
 #define TT_ILL_INSN 0x02
+#define TT_PRIV_INSN 0x03
 #define TT_WIN_OVF  0x05
 #define TT_WIN_UNF  0x06 
+#define TT_FP_EXCP  0x08
 #define TT_DIV_ZERO 0x2a
 #define TT_TRAP     0x80
 
@@ -18,27 +20,101 @@
 #define PSR_ZERO  (1<<22)
 #define PSR_OVF   (1<<21)
 #define PSR_CARRY (1<<20)
+#define PSR_ICC   (PSR_NEG|PSR_ZERO|PSR_OVF|PSR_CARRY)
+#define PSR_S     (1<<7)
+#define PSR_PS    (1<<6)
+#define PSR_ET    (1<<5)
+#define PSR_CWP   0x1f
+/* Fake impl 0, version 4 */
+#define GET_PSR(env) ((0<<28) | (4<<24) | env->psr | (env->psrs? PSR_S : 0) | (env->psrs? PSR_PS : 0) |(env->psret? PSR_ET : 0) | env->cwp)
+
+/* Trap base register */
+#define TBR_BASE_MASK 0xfffff000
+
+/* Fcc */
+#define FSR_RD1        (1<<31)
+#define FSR_RD0        (1<<30)
+#define FSR_RD_MASK    (FSR_RD1 | FSR_RD0)
+#define FSR_RD_NEAREST 0
+#define FSR_RD_ZERO    FSR_RD0
+#define FSR_RD_POS     FSR_RD1
+#define FSR_RD_NEG     (FSR_RD1 | FSR_RD0)
+
+#define FSR_NVM   (1<<27)
+#define FSR_OFM   (1<<26)
+#define FSR_UFM   (1<<25)
+#define FSR_DZM   (1<<24)
+#define FSR_NXM   (1<<23)
+#define FSR_TEM_MASK (FSR_NVM | FSR_OFM | FSR_UFM | FSR_DZM | FSR_NXM)
+
+#define FSR_NVA   (1<<9)
+#define FSR_OFA   (1<<8)
+#define FSR_UFA   (1<<7)
+#define FSR_DZA   (1<<6)
+#define FSR_NXA   (1<<5)
+#define FSR_AEXC_MASK (FSR_NVA | FSR_OFA | FSR_UFA | FSR_DZA | FSR_NXA)
+
+#define FSR_NVC   (1<<4)
+#define FSR_OFC   (1<<3)
+#define FSR_UFC   (1<<2)
+#define FSR_DZC   (1<<1)
+#define FSR_NXC   (1<<0)
+#define FSR_CEXC_MASK (FSR_NVC | FSR_OFC | FSR_UFC | FSR_DZC | FSR_NXC)
+
+#define FSR_FTT2   (1<<16)
+#define FSR_FTT1   (1<<15)
+#define FSR_FTT0   (1<<14)
+#define FSR_FTT_MASK (FSR_FTT2 | FSR_FTT1 | FSR_FTT0)
+
+#define FSR_FCC1  (1<<11)
+#define FSR_FCC0  (1<<10)
+
+/* MMU */
+#define MMU_E	  (1<<0)
+#define MMU_NF	  (1<<1)
+
+#define PTE_ENTRYTYPE_MASK 3
+#define PTE_ACCESS_MASK    0x1c
+#define PTE_ACCESS_SHIFT   2
+#define PTE_ADDR_MASK      0xffffff00
+
+#define PG_ACCESSED_BIT	5
+#define PG_MODIFIED_BIT	6
+#define PG_CACHE_BIT    7
+
+#define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT)
+#define PG_MODIFIED_MASK (1 << PG_MODIFIED_BIT)
+#define PG_CACHE_MASK    (1 << PG_CACHE_BIT)
+
+#define ACCESS_DATA	0
+#define ACCESS_CODE	1
+#define ACCESS_MMU	2
 
 #define NWINDOWS  32
 
 typedef struct CPUSPARCState {
     uint32_t gregs[8]; /* general registers */
     uint32_t *regwptr; /* pointer to current register window */
-    double   *regfptr; /* floating point registers */
+    float    fpr[32];  /* floating point registers */
     uint32_t pc;       /* program counter */
     uint32_t npc;      /* next program counter */
-    uint32_t sp;       /* stack pointer */
     uint32_t y;        /* multiply/divide register */
     uint32_t psr;      /* processor state register */
+    uint32_t fsr;      /* FPU state register */
     uint32_t T2;
     uint32_t cwp;      /* index of current register window (extracted
                           from PSR) */
     uint32_t wim;      /* window invalid mask */
+    uint32_t tbr;      /* trap base register */
+    int      psrs;     /* supervisor mode (extracted from PSR) */
+    int      psrps;    /* previous supervisor mode */
+    int      psret;    /* enable traps */
     jmp_buf  jmp_env;
     int user_mode_only;
     int exception_index;
     int interrupt_index;
     int interrupt_request;
+    uint32_t exception_next_pc;
     struct TranslationBlock *current_tb;
     void *opaque;
     /* NOTE: we allow 8 more registers to handle wrapping */
@@ -51,6 +127,22 @@ typedef struct CPUSPARCState {
                                    written */
     unsigned long mem_write_vaddr; /* target virtual addr at which the
                                       memory was written */
+    /* 0 = kernel, 1 = user (may have 2 = kernel code, 3 = user code ?) */
+    CPUTLBEntry tlb_read[2][CPU_TLB_SIZE];
+    CPUTLBEntry tlb_write[2][CPU_TLB_SIZE];
+    int error_code;
+    int access_type;
+    /* MMU regs */
+    uint32_t mmuregs[16];
+    /* temporary float registers */
+    float ft0, ft1, ft2;
+    double dt0, dt1, dt2;
+
+    /* ice debug support */
+    uint32_t breakpoints[MAX_BREAKPOINTS];
+    int nb_breakpoints;
+    int singlestep_enabled; /* XXX: should use CPU single step mode instead */
+
 } CPUSPARCState;
 
 CPUSPARCState *cpu_sparc_init(void);
@@ -61,7 +153,7 @@ struct siginfo;
 int cpu_sparc_signal_handler(int hostsignum, struct siginfo *info, void *puc);
 void cpu_sparc_dump_state(CPUSPARCState *env, FILE *f, int flags);
 
-#define TARGET_PAGE_BITS 13
+#define TARGET_PAGE_BITS 12 /* 4k */
 #include "cpu-all.h"
 
 #endif

target-sparc/exec.h

@@ -6,6 +6,12 @@ register struct CPUSPARCState *env asm(AREG0);
 register uint32_t T0 asm(AREG1);
 register uint32_t T1 asm(AREG2);
 register uint32_t T2 asm(AREG3);
+#define FT0 (env->ft0)
+#define FT1 (env->ft1)
+#define FT2 (env->ft2)
+#define DT0 (env->dt0)
+#define DT1 (env->dt1)
+#define DT2 (env->dt2)
 
 #include "cpu.h"
 #include "exec-all.h"
@@ -14,4 +20,88 @@ void cpu_lock(void);
 void cpu_unlock(void);
 void cpu_loop_exit(void);
 void helper_flush(target_ulong addr);
+void helper_ld_asi(int asi, int size, int sign);
+void helper_st_asi(int asi, int size, int sign);
+void helper_rett(void);
+void helper_stfsr(void);
+void set_cwp(int new_cwp);
+void do_fabss(void);
+void do_fsqrts(void);
+void do_fsqrtd(void);
+void do_fcmps(void);
+void do_fcmpd(void);
+void do_interrupt(int intno, int is_int, int error_code, 
+                  unsigned int next_eip, int is_hw);
+void raise_exception_err(int exception_index, int error_code);
+void raise_exception(int tt);
+void memcpy32(uint32_t *dst, const uint32_t *src);
+
+/* XXX: move that to a generic header */
+#if !defined(CONFIG_USER_ONLY)
+
+#define ldul_user ldl_user
+#define ldul_kernel ldl_kernel
+
+#define ACCESS_TYPE 0
+#define MEMSUFFIX _kernel
+#define DATA_SIZE 1
+#include "softmmu_header.h"
+
+#define DATA_SIZE 2
+#include "softmmu_header.h"
+
+#define DATA_SIZE 4
+#include "softmmu_header.h"
+
+#define DATA_SIZE 8
+#include "softmmu_header.h"
+#undef ACCESS_TYPE
+#undef MEMSUFFIX
+
+#define ACCESS_TYPE 1
+#define MEMSUFFIX _user
+#define DATA_SIZE 1
+#include "softmmu_header.h"
+
+#define DATA_SIZE 2
+#include "softmmu_header.h"
+
+#define DATA_SIZE 4
+#include "softmmu_header.h"
+
+#define DATA_SIZE 8
+#include "softmmu_header.h"
+#undef ACCESS_TYPE
+#undef MEMSUFFIX
+
+/* these access are slower, they must be as rare as possible */
+#define ACCESS_TYPE 2
+#define MEMSUFFIX _data
+#define DATA_SIZE 1
+#include "softmmu_header.h"
+
+#define DATA_SIZE 2
+#include "softmmu_header.h"
+
+#define DATA_SIZE 4
+#include "softmmu_header.h"
+
+#define DATA_SIZE 8
+#include "softmmu_header.h"
+#undef ACCESS_TYPE
+#undef MEMSUFFIX
+
+#define ldub(p) ldub_data(p)
+#define ldsb(p) ldsb_data(p)
+#define lduw(p) lduw_data(p)
+#define ldsw(p) ldsw_data(p)
+#define ldl(p) ldl_data(p)
+#define ldq(p) ldq_data(p)
+
+#define stb(p, v) stb_data(p, v)
+#define stw(p, v) stw_data(p, v)
+#define stl(p, v) stl_data(p, v)
+#define stq(p, v) stq_data(p, v)
+
+#endif /* !defined(CONFIG_USER_ONLY) */
 #endif

target-sparc/fop_template.h

+/*
+ *  SPARC micro operations (templates for various register related
+ *  operations)
+ * 
+ *  Copyright (c) 2003 Fabrice Bellard
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+/* floating point registers moves */
+void OPPROTO glue(op_load_fpr_FT0_fpr, REGNAME)(void)
+{
+    FT0 = REG;
+}
+
+void OPPROTO glue(op_store_FT0_fpr_fpr, REGNAME)(void)
+{
+    REG = FT0;
+}
+
+void OPPROTO glue(op_load_fpr_FT1_fpr, REGNAME)(void)
+{
+    FT1 = REG;
+}
+
+void OPPROTO glue(op_store_FT1_fpr_fpr, REGNAME)(void)
+{
+    REG = FT1;
+}
+
+void OPPROTO glue(op_load_fpr_FT2_fpr, REGNAME)(void)
+{
+    FT2 = REG;
+}
+
+void OPPROTO glue(op_store_FT2_fpr_fpr, REGNAME)(void)
+{
+    REG = FT2;
+}
+
+/* double floating point registers moves */
+#if 0
+#define CPU_DOUBLE_U_DEF
+typedef union {
+    double d;
+    struct {
+        uint32_t lower;
+        uint32_t upper;
+    } l;
+    uint64_t ll;
+} CPU_DoubleU;
+#endif /* CPU_DOUBLE_U_DEF */
+
+void OPPROTO glue(op_load_fpr_DT0_fpr, REGNAME)(void)
+{
+    CPU_DoubleU u;
+    uint32_t *p = (uint32_t *)®
+    u.l.lower = *(p +1);
+    u.l.upper = *p;
+    DT0 = u.d;
+}
+
+void OPPROTO glue(op_store_DT0_fpr_fpr, REGNAME)(void)
+{
+    CPU_DoubleU u;
+    uint32_t *p = (uint32_t *)®
+    u.d = DT0;
+    *(p +1) = u.l.lower;
+    *p = u.l.upper;
+}
+
+void OPPROTO glue(op_load_fpr_DT1_fpr, REGNAME)(void)
+{
+    CPU_DoubleU u;
+    uint32_t *p = (uint32_t *)®
+    u.l.lower = *(p +1);
+    u.l.upper = *p;
+    DT1 = u.d;
+}
+
+void OPPROTO glue(op_store_DT1_fpr_fpr, REGNAME)(void)
+{
+    CPU_DoubleU u;
+    uint32_t *p = (uint32_t *)®
+    u.d = DT1;
+    *(p +1) = u.l.lower;
+    *p = u.l.upper;
+}
+
+void OPPROTO glue(op_load_fpr_DT2_fpr, REGNAME)(void)
+{
+    CPU_DoubleU u;
+    uint32_t *p = (uint32_t *)®
+    u.l.lower = *(p +1);
+    u.l.upper = *p;
+    DT2 = u.d;
+}
+
+void OPPROTO glue(op_store_DT2_fpr_fpr, REGNAME)(void)
+{
+    CPU_DoubleU u;
+    uint32_t *p = (uint32_t *)®
+    u.d = DT2;
+    *(p +1) = u.l.lower;
+    *p = u.l.upper;
+}
+
+#undef REG
+#undef REGNAME

target-sparc/helper.c

+/*
+ *  sparc helpers
+ * 
+ *  Copyright (c) 2003 Fabrice Bellard
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#include "exec.h"
+
+#define DEBUG_PCALL
+
+#if 0
+#define raise_exception_err(a, b)\
+do {\
+    fprintf(logfile, "raise_exception line=%d\n", __LINE__);\
+    (raise_exception_err)(a, b);\
+} while (0)
+#endif
+
+/* Sparc MMU emulation */
+int cpu_sparc_handle_mmu_fault (CPUState *env, uint32_t address, int rw,
+                              int is_user, int is_softmmu);
+
+
+/* thread support */
+
+spinlock_t global_cpu_lock = SPIN_LOCK_UNLOCKED;
+
+void cpu_lock(void)
+{
+    spin_lock(&global_cpu_lock);
+}
+
+void cpu_unlock(void)
+{
+    spin_unlock(&global_cpu_lock);
+}
+
+#if 0
+void cpu_loop_exit(void)
+{
+    /* NOTE: the register at this point must be saved by hand because
+       longjmp restore them */
+    longjmp(env->jmp_env, 1);
+}
+#endif
+
+#if !defined(CONFIG_USER_ONLY) 
+
+#define MMUSUFFIX _mmu
+#define GETPC() (__builtin_return_address(0))
+
+#define SHIFT 0
+#include "softmmu_template.h"
+
+#define SHIFT 1
+#include "softmmu_template.h"
+
+#define SHIFT 2
+#include "softmmu_template.h"
+
+#define SHIFT 3
+#include "softmmu_template.h"
+
+
+/* try to fill the TLB and return an exception if error. If retaddr is
+   NULL, it means that the function was called in C code (i.e. not
+   from generated code or from helper.c) */
+/* XXX: fix it to restore all registers */
+void tlb_fill(unsigned long addr, int is_write, int is_user, void *retaddr)
+{
+    TranslationBlock *tb;
+    int ret;
+    unsigned long pc;
+    CPUState *saved_env;
+
+    /* XXX: hack to restore env in all cases, even if not called from
+       generated code */
+    saved_env = env;
+    env = cpu_single_env;
+
+    ret = cpu_sparc_handle_mmu_fault(env, addr, is_write, is_user, 1);
+    if (ret) {
+        if (retaddr) {
+            /* now we have a real cpu fault */
+            pc = (unsigned long)retaddr;
+            tb = tb_find_pc(pc);
+            if (tb) {
+                /* the PC is inside the translated code. It means that we have
+                   a virtual CPU fault */
+                cpu_restore_state(tb, env, pc, NULL);
+            }
+        }
+        raise_exception_err(ret, env->error_code);
+    }
+    env = saved_env;
+}
+#endif
+
+static const int access_table[8][8] = {
+    { 0, 0, 0, 0, 2, 0, 3, 3 },
+    { 0, 0, 0, 0, 2, 0, 0, 0 },
+    { 2, 2, 0, 0, 0, 2, 3, 3 },
+    { 2, 2, 0, 0, 0, 2, 0, 0 },
+    { 2, 0, 2, 0, 2, 2, 3, 3 },
+    { 2, 0, 2, 0, 2, 0, 2, 0 },
+    { 2, 2, 2, 0, 2, 2, 3, 3 },
+    { 2, 2, 2, 0, 2, 2, 2, 0 }
+};
+
+/* 1 = write OK */
+static const int rw_table[2][8] = {
+    { 0, 1, 0, 1, 0, 1, 0, 1 },
+    { 0, 1, 0, 1, 0, 0, 0, 0 }
+};
+
+
+/* Perform address translation */
+int cpu_sparc_handle_mmu_fault (CPUState *env, uint32_t address, int rw,
+                              int is_user, int is_softmmu)
+{
+    int exception = 0;
+    int access_type, access_perms = 0, access_index = 0;
+    uint8_t *pde_ptr;
+    uint32_t pde, virt_addr;
+    int error_code = 0, is_dirty, prot, ret = 0;
+    unsigned long paddr, vaddr, page_offset;
+
+    access_type = env->access_type;
+    if (env->user_mode_only) {
+        /* user mode only emulation */
+        ret = -2;
+        goto do_fault;
+    }
+
+    virt_addr = address & TARGET_PAGE_MASK;
+    if ((env->mmuregs[0] & MMU_E) == 0) { /* MMU disabled */
+	paddr = address;
+	page_offset = address & (TARGET_PAGE_SIZE - 1);
+        prot = PAGE_READ | PAGE_WRITE;
+        goto do_mapping;
+    }
+
+    /* SPARC reference MMU table walk: Context table->L1->L2->PTE */
+    /* Context base + context number */
+    pde_ptr = phys_ram_base + (env->mmuregs[1] << 4) + (env->mmuregs[2] << 4);
+    env->access_type = ACCESS_MMU;
+    pde = ldl_raw(pde_ptr);
+
+    /* Ctx pde */
+    switch (pde & PTE_ENTRYTYPE_MASK) {
+    case 0: /* Invalid */
+        error_code = 1;
+        goto do_fault;
+    case 2: /* PTE, maybe should not happen? */
+    case 3: /* Reserved */
+        error_code = 4;
+        goto do_fault;
+    case 1: /* L1 PDE */
+	pde_ptr = phys_ram_base + ((address >> 22) & ~3) + ((pde & ~3) << 4);
+	pde = ldl_raw(pde_ptr);
+
+	switch (pde & PTE_ENTRYTYPE_MASK) {
+	case 0: /* Invalid */
+	    error_code = 1;
+	    goto do_fault;
+	case 3: /* Reserved */
+	    error_code = 4;
+	    goto do_fault;
+	case 1: /* L2 PDE */
+	    pde_ptr = phys_ram_base + ((address & 0xfc0000) >> 16) + ((pde & ~3) << 4);
+	    pde = ldl_raw(pde_ptr);
+
+	    switch (pde & PTE_ENTRYTYPE_MASK) {
+	    case 0: /* Invalid */
+		error_code = 1;
+		goto do_fault;
+	    case 3: /* Reserved */
+		error_code = 4;
+		goto do_fault;
+	    case 1: /* L3 PDE */
+		pde_ptr = phys_ram_base + ((address & 0x3f000) >> 10) + ((pde & ~3) << 4);
+		pde = ldl_raw(pde_ptr);
+
+		switch (pde & PTE_ENTRYTYPE_MASK) {
+		case 0: /* Invalid */
+		    error_code = 1;
+		    goto do_fault;
+		case 1: /* PDE, should not happen */
+		case 3: /* Reserved */
+		    error_code = 4;
+		    goto do_fault;
+		case 2: /* L3 PTE */
+		    virt_addr = address & TARGET_PAGE_MASK;
+		    page_offset = (address & TARGET_PAGE_MASK) & (TARGET_PAGE_SIZE - 1);
+		}
+		break;
+	    case 2: /* L2 PTE */
+		virt_addr = address & ~0x3ffff;
+		page_offset = address & 0x3ffff;
+	    }
+	    break;
+	case 2: /* L1 PTE */
+	    virt_addr = address & ~0xffffff;
+	    page_offset = address & 0xffffff;
+	}
+    }
+
+    /* update page modified and dirty bits */
+    is_dirty = rw && !(pde & PG_MODIFIED_MASK);
+    if (!(pde & PG_ACCESSED_MASK) || is_dirty) {
+	pde |= PG_ACCESSED_MASK;
+	if (is_dirty)
+	    pde |= PG_MODIFIED_MASK;
+	stl_raw(pde_ptr, pde);
+    }
+
+    /* check access */
+    access_index = (rw << 2) | ((access_type == ACCESS_CODE)? 2 : 0) | (is_user? 0 : 1);
+    access_perms = (pde & PTE_ACCESS_MASK) >> PTE_ACCESS_SHIFT;
+    error_code = access_table[access_index][access_perms];
+    if (error_code)
+	goto do_fault;
+
+    /* the page can be put in the TLB */
+    prot = PAGE_READ;
+    if (pde & PG_MODIFIED_MASK) {
+        /* only set write access if already dirty... otherwise wait
+           for dirty access */
+	if (rw_table[is_user][access_perms])
+	        prot |= PAGE_WRITE;
+    }
+
+    /* Even if large ptes, we map only one 4KB page in the cache to
+       avoid filling it too fast */
+    virt_addr = address & TARGET_PAGE_MASK;
+    paddr = ((pde & PTE_ADDR_MASK) << 4) + page_offset;
+
+ do_mapping:
+    env->access_type = access_type;
+    vaddr = virt_addr + ((address & TARGET_PAGE_MASK) & (TARGET_PAGE_SIZE - 1));
+
+    ret = tlb_set_page(env, vaddr, paddr, prot, is_user, is_softmmu);
+    return ret;
+
+ do_fault:
+    env->access_type = access_type;
+    if (env->mmuregs[3]) /* Fault status register */
+	env->mmuregs[3] = 1; /* overflow (not read before another fault) */
+    env->mmuregs[3] |= (access_index << 5) | (error_code << 2) | 2;
+    env->mmuregs[4] = address; /* Fault address register */
+