Commit e0353fe2 authored by blueswir1's avatar blueswir1
Browse files

Add SparcStation-10 machine


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2571 c046a42c-6fe2-441c-8c8c-71466251a162
parent 36cd9210
......@@ -54,6 +54,7 @@ typedef struct SLAVIO_INTCTLState {
uint64_t irq_count[32];
#endif
CPUState *cpu_envs[MAX_CPUS];
const uint32_t *intbit_to_level;
} SLAVIO_INTCTLState;
#define INTCTL_MAXADDR 0xf
......@@ -208,11 +209,6 @@ void slavio_irq_info(void *opaque)
#endif
}
static const uint32_t intbit_to_level[32] = {
2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
};
static void slavio_check_interrupts(void *opaque)
{
CPUState *env;
......@@ -225,8 +221,8 @@ static void slavio_check_interrupts(void *opaque)
if (pending && !(s->intregm_disabled & 0x80000000)) {
for (i = 0; i < 32; i++) {
if (pending & (1 << i)) {
if (max < intbit_to_level[i])
max = intbit_to_level[i];
if (max < s->intbit_to_level[i])
max = s->intbit_to_level[i];
}
}
env = s->cpu_envs[s->target_cpu];
......@@ -288,7 +284,7 @@ void slavio_pic_set_irq(void *opaque, int irq, int level)
DPRINTF("Set cpu %d irq %d level %d\n", s->target_cpu, irq, level);
if (irq < 32) {
uint32_t mask = 1 << irq;
uint32_t pil = intbit_to_level[irq];
uint32_t pil = s->intbit_to_level[irq];
if (pil > 0) {
if (level) {
s->intregm_pending |= mask;
......@@ -313,7 +309,7 @@ void slavio_pic_set_irq_cpu(void *opaque, int irq, int level, unsigned int cpu)
return;
}
if (irq < 32) {
uint32_t pil = intbit_to_level[irq];
uint32_t pil = s->intbit_to_level[irq];
if (pil > 0) {
if (level) {
s->intreg_pending[cpu] |= 1 << pil;
......@@ -375,7 +371,8 @@ void slavio_intctl_set_cpu(void *opaque, unsigned int cpu, CPUState *env)
s->cpu_envs[cpu] = env;
}
void *slavio_intctl_init(uint32_t addr, uint32_t addrg)
void *slavio_intctl_init(uint32_t addr, uint32_t addrg,
const uint32_t *intbit_to_level)
{
int slavio_intctl_io_memory, slavio_intctlm_io_memory, i;
SLAVIO_INTCTLState *s;
......@@ -384,6 +381,7 @@ void *slavio_intctl_init(uint32_t addr, uint32_t addrg)
if (!s)
return NULL;
s->intbit_to_level = intbit_to_level;
for (i = 0; i < MAX_CPUS; i++) {
slavio_intctl_io_memory = cpu_register_io_memory(0, slavio_intctl_mem_read, slavio_intctl_mem_write, s);
cpu_register_physical_memory(addr + i * TARGET_PAGE_SIZE, INTCTL_MAXADDR, slavio_intctl_io_memory);
......
......@@ -59,6 +59,7 @@ struct hwdef {
int intctl_g_intr, esp_irq, le_irq, cpu_irq, clock_irq, clock1_irq;
int ser_irq, ms_kb_irq, fd_irq, me_irq, cs_irq;
int machine_id; // For NVRAM
uint32_t intbit_to_level[32];
};
/* TSC handling */
......@@ -238,7 +239,8 @@ static void sun4m_hw_init(const struct hwdef *hwdef, int ram_size,
iommu = iommu_init(hwdef->iommu_base);
slavio_intctl = slavio_intctl_init(hwdef->intctl_base,
hwdef->intctl_base + 0x10000);
hwdef->intctl_base + 0x10000,
&hwdef->intbit_to_level[0]);
for(i = 0; i < smp_cpus; i++) {
slavio_intctl_set_cpu(slavio_intctl, i, envs[i]);
}
......@@ -375,6 +377,43 @@ static const struct hwdef hwdefs[] = {
.me_irq = 30,
.cs_irq = 5,
.machine_id = 0x80,
.intbit_to_level = {
2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
},
},
/* SS-10 */
/* XXX: Replace with real values */
{
.iommu_base = 0x10000000,
.tcx_base = 0x50000000,
.cs_base = 0x6c000000,
.slavio_base = 0x71000000,
.ms_kb_base = 0x71000000,
.serial_base = 0x71100000,
.nvram_base = 0x71200000,
.fd_base = 0x71400000,
.counter_base = 0x71d00000,
.intctl_base = 0x71e00000,
.dma_base = 0x78400000,
.esp_base = 0x78800000,
.le_base = 0x78c00000,
.vram_size = 0x00100000,
.nvram_size = 0x2000,
.esp_irq = 18,
.le_irq = 16,
.clock_irq = 7,
.clock1_irq = 19,
.ms_kb_irq = 14,
.ser_irq = 15,
.fd_irq = 22,
.me_irq = 30,
.cs_irq = 5,
.machine_id = 0x73,
.intbit_to_level = {
2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
},
},
};
......@@ -403,8 +442,27 @@ static void ss5_init(int ram_size, int vga_ram_size, int boot_device,
0);
}
/* SPARCstation 10 hardware initialisation */
static void ss10_init(int ram_size, int vga_ram_size, int boot_device,
DisplayState *ds, const char **fd_filename, int snapshot,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
if (cpu_model == NULL)
cpu_model = "TI SuperSparc II";
sun4m_common_init(ram_size, boot_device, ds, kernel_filename,
kernel_cmdline, initrd_filename, cpu_model,
1);
}
QEMUMachine ss5_machine = {
"SS-5",
"Sun4m platform, SPARCstation 5",
ss5_init,
};
QEMUMachine ss10_machine = {
"SS-10",
"Sun4m platform, SPARCstation 10",
ss10_init,
};
......@@ -2874,6 +2874,13 @@ static const sparc_def_t sparc_defs[] = {
.fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
.mmu_version = 0x04 << 24, /* Impl 0, ver 4 */
},
{
/* XXX: Replace with real values */
.name = "TI SuperSparc II",
.iu_version = 0x40000000,
.fpu_version = 0x00000000,
.mmu_version = 0x00000000,
},
#endif
};
......
......@@ -6691,6 +6691,7 @@ void register_machines(void)
qemu_register_machine(&sun4u_machine);
#else
qemu_register_machine(&ss5_machine);
qemu_register_machine(&ss10_machine);
#endif
#elif defined(TARGET_ARM)
qemu_register_machine(&integratorcp_machine);
......
......@@ -1143,7 +1143,7 @@ extern CPUReadMemoryFunc *PPC_io_read[];
void PPC_debug_write (void *opaque, uint32_t addr, uint32_t val);
/* sun4m.c */
extern QEMUMachine ss5_machine;
extern QEMUMachine ss5_machine, ss10_machine;
void pic_set_irq_cpu(int irq, int level, unsigned int cpu);
/* iommu.c */
......@@ -1169,7 +1169,8 @@ void tcx_init(DisplayState *ds, uint32_t addr, uint8_t *vram_base,
unsigned long vram_offset, int vram_size, int width, int height);
/* slavio_intctl.c */
void *slavio_intctl_init(uint32_t addr, uint32_t addrg);
void *slavio_intctl_init(uint32_t addr, uint32_t addrg,
const uint32_t *intbit_to_level);
void slavio_intctl_set_cpu(void *opaque, unsigned int cpu, CPUState *env);
void slavio_pic_info(void *opaque);
void slavio_irq_info(void *opaque);
......
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