Commit d7d02e3c authored by bellard's avatar bellard
Browse files

new reset API


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@938 c046a42c-6fe2-441c-8c8c-71466251a162
parent bb0c6722
......@@ -355,6 +355,12 @@ void DMA_schedule(int nchan)
cpu_interrupt(cpu_single_env, CPU_INTERRUPT_EXIT);
}
static void dma_reset(void *opaque)
{
struct dma_cont *d = opaque;
write_cont (d, (0x0d << d->dshift), 0);
}
/* dshift = 0: 8 bit DMA, 1 = 16 bit DMA */
static void dma_init2(struct dma_cont *d, int base, int dshift, int page_base)
{
......@@ -378,7 +384,8 @@ static void dma_init2(struct dma_cont *d, int base, int dshift, int page_base)
register_ioport_read (base + ((i + 8) << dshift), 1, 1,
read_cont, d);
}
write_cont (d, base + (0x0d << dshift), 0);
qemu_register_reset(dma_reset, d);
dma_reset(d);
}
void DMA_init (void)
......
......@@ -434,27 +434,37 @@ static int pit_load(QEMUFile *f, void *opaque, int version_id)
return 0;
}
PITState *pit_init(int base, int irq)
static void pit_reset(void *opaque)
{
PITState *pit = &pit_state;
PITState *pit = opaque;
PITChannelState *s;
int i;
for(i = 0;i < 3; i++) {
s = &pit->channels[i];
if (i == 0) {
/* the timer 0 is connected to an IRQ */
s->irq_timer = qemu_new_timer(vm_clock, pit_irq_timer, s);
s->irq = irq;
}
s->mode = 3;
s->gate = (i != 2);
pit_load_count(s, 0);
}
}
PITState *pit_init(int base, int irq)
{
PITState *pit = &pit_state;
PITChannelState *s;
s = &pit->channels[0];
/* the timer 0 is connected to an IRQ */
s->irq_timer = qemu_new_timer(vm_clock, pit_irq_timer, s);
s->irq = irq;
register_savevm("i8254", base, 1, pit_save, pit_load, pit);
qemu_register_reset(pit_reset, pit);
register_ioport_write(base, 4, 1, pit_ioport_write, pit);
register_ioport_read(base, 3, 1, pit_ioport_read, pit);
pit_reset(pit);
return pit;
}
......@@ -231,10 +231,20 @@ int cpu_get_pic_interrupt(CPUState *env)
return intno;
}
static void pic_reset(void *opaque)
{
PicState *s = opaque;
int tmp;
tmp = s->elcr_mask;
memset(s, 0, sizeof(PicState));
s->elcr_mask = tmp;
}
static void pic_ioport_write(void *opaque, uint32_t addr, uint32_t val)
{
PicState *s = opaque;
int priority, cmd, irq, tmp;
int priority, cmd, irq;
#ifdef DEBUG_PIC
printf("pic_write: addr=0x%02x val=0x%02x\n", addr, val);
......@@ -243,9 +253,7 @@ static void pic_ioport_write(void *opaque, uint32_t addr, uint32_t val)
if (addr == 0) {
if (val & 0x10) {
/* init */
tmp = s->elcr_mask;
memset(s, 0, sizeof(PicState));
s->elcr_mask = tmp;
pic_reset(s);
/* deassert a pending interrupt */
cpu_reset_interrupt(cpu_single_env, CPU_INTERRUPT_HARD);
......@@ -458,6 +466,7 @@ static void pic_init1(int io_addr, int elcr_addr, PicState *s)
register_ioport_read(elcr_addr, 1, 1, elcr_ioport_read, s);
}
register_savevm("i8259", io_addr, 1, pic_save, pic_load, s);
qemu_register_reset(pic_reset, s);
}
void pic_info(void)
......
......@@ -162,9 +162,7 @@ static void watchdog_cb (void *opaque)
NVRAM->buffer[0x1FF7] = 0x00;
NVRAM->buffer[0x1FFC] &= ~0x40;
/* May it be a hw CPU Reset instead ? */
reset_requested = 1;
printf("Watchdog reset...\n");
cpu_interrupt(cpu_single_env, CPU_INTERRUPT_EXIT);
qemu_system_reset_request();
} else {
pic_set_irq(NVRAM->IRQ, 1);
pic_set_irq(NVRAM->IRQ, 0);
......
......@@ -139,7 +139,6 @@ typedef struct KBDState {
} KBDState;
KBDState kbd_state;
int reset_requested;
/* update irq and KBD_STAT_[MOUSE_]OBF */
/* XXX: not generating the irqs if KBD_MODE_DISABLE_KBD is set may be
......@@ -274,8 +273,7 @@ static void kbd_write_command(void *opaque, uint32_t addr, uint32_t val)
break;
#endif
case KBD_CCMD_RESET:
reset_requested = 1;
cpu_interrupt(cpu_single_env, CPU_INTERRUPT_EXIT);
qemu_system_reset_request();
break;
case 0xff:
/* ignore that - I don't know what is its use */
......@@ -617,8 +615,7 @@ void kbd_write_data(void *opaque, uint32_t addr, uint32_t val)
cpu_x86_set_a20(cpu_single_env, (val >> 1) & 1);
#endif
if (!(val & 1)) {
reset_requested = 1;
cpu_interrupt(cpu_single_env, CPU_INTERRUPT_EXIT);
qemu_system_reset_request();
}
break;
case KBD_CCMD_WRITE_MOUSE:
......@@ -630,8 +627,9 @@ void kbd_write_data(void *opaque, uint32_t addr, uint32_t val)
s->write_cmd = 0;
}
void kbd_reset(KBDState *s)
static void kbd_reset(void *opaque)
{
KBDState *s = opaque;
KBDQueue *q;
s->kbd_write_cmd = -1;
......@@ -656,4 +654,5 @@ void kbd_init(void)
qemu_add_kbd_event_handler(pc_kbd_put_keycode, s);
qemu_add_mouse_event_handler(pc_kbd_mouse_event, s);
qemu_register_reset(kbd_reset, s);
}
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