Commit d720b93d authored by bellard's avatar bellard
Browse files

precise self modifying code support


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@745 c046a42c-6fe2-441c-8c8c-71466251a162
parent eeab3a55
......@@ -681,8 +681,7 @@ extern uint8_t *phys_ram_dirty;
#define IO_MEM_CODE (3 << IO_MEM_SHIFT) /* used internally, never use directly */
#define IO_MEM_NOTDIRTY (4 << IO_MEM_SHIFT) /* used internally, never use directly */
/* NOTE: vaddr is only used internally. Never use it except if you know what you do */
typedef void CPUWriteMemoryFunc(uint32_t addr, uint32_t value, uint32_t vaddr);
typedef void CPUWriteMemoryFunc(uint32_t addr, uint32_t value);
typedef uint32_t CPUReadMemoryFunc(uint32_t addr);
void cpu_register_physical_memory(unsigned long start_addr, unsigned long size,
......
This diff is collapsed.
......@@ -70,20 +70,23 @@ static inline DATA_TYPE glue(io_read, SUFFIX)(unsigned long physaddr,
static inline void glue(io_write, SUFFIX)(unsigned long physaddr,
DATA_TYPE val,
unsigned long tlb_addr)
unsigned long tlb_addr,
void *retaddr)
{
int index;
index = (tlb_addr >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
env->mem_write_vaddr = tlb_addr;
env->mem_write_pc = (unsigned long)retaddr;
#if SHIFT <= 2
io_mem_write[index][SHIFT](physaddr, val, tlb_addr);
io_mem_write[index][SHIFT](physaddr, val);
#else
#ifdef TARGET_WORDS_BIGENDIAN
io_mem_write[index][2](physaddr, val >> 32, tlb_addr);
io_mem_write[index][2](physaddr + 4, val, tlb_addr);
io_mem_write[index][2](physaddr, val >> 32);
io_mem_write[index][2](physaddr + 4, val);
#else
io_mem_write[index][2](physaddr, val, tlb_addr);
io_mem_write[index][2](physaddr + 4, val >> 32, tlb_addr);
io_mem_write[index][2](physaddr, val);
io_mem_write[index][2](physaddr + 4, val >> 32);
#endif
#endif /* SHIFT > 2 */
}
......@@ -193,7 +196,8 @@ void REGPARM(2) glue(glue(__st, SUFFIX), MMUSUFFIX)(unsigned long addr,
/* IO access */
if ((addr & (DATA_SIZE - 1)) != 0)
goto do_unaligned_access;
glue(io_write, SUFFIX)(physaddr, val, tlb_addr);
retaddr = GETPC();
glue(io_write, SUFFIX)(physaddr, val, tlb_addr, retaddr);
} else if (((addr & 0xfff) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) {
do_unaligned_access:
retaddr = GETPC();
......@@ -229,7 +233,7 @@ static void glue(glue(slow_st, SUFFIX), MMUSUFFIX)(unsigned long addr,
/* IO access */
if ((addr & (DATA_SIZE - 1)) != 0)
goto do_unaligned_access;
glue(io_write, SUFFIX)(physaddr, val, tlb_addr);
glue(io_write, SUFFIX)(physaddr, val, tlb_addr, retaddr);
} else if (((addr & 0xfff) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) {
do_unaligned_access:
/* XXX: not efficient, but simple */
......
......@@ -43,6 +43,13 @@ typedef struct CPUARMState {
struct TranslationBlock *current_tb;
int user_mode_only;
/* in order to avoid passing too many arguments to the memory
write helpers, we store some rarely used information in the CPU
context) */
unsigned long mem_write_pc; /* host pc at which the memory was
written */
unsigned long mem_write_vaddr; /* target virtual addr at which the
memory was written */
/* user data */
void *opaque;
} CPUARMState;
......
......@@ -22,6 +22,12 @@
#define TARGET_LONG_BITS 32
/* target supports implicit self modifying code */
#define TARGET_HAS_SMC
/* support for self modifying code even if the modified instruction is
close to the modifying instruction */
#define TARGET_HAS_PRECISE_SMC
#include "cpu-defs.h"
#if defined(__i386__) && !defined(CONFIG_SOFTMMU)
......@@ -331,8 +337,16 @@ typedef struct CPUX86State {
int interrupt_request;
int user_mode_only; /* user mode only simulation */
/* soft mmu support */
uint32_t a20_mask;
/* soft mmu support */
/* in order to avoid passing too many arguments to the memory
write helpers, we store some rarely used information in the CPU
context) */
unsigned long mem_write_pc; /* host pc at which the memory was
written */
unsigned long mem_write_vaddr; /* target virtual addr at which the
memory was written */
/* 0 = kernel, 1 = user */
CPUTLBEntry tlb_read[2][CPU_TLB_SIZE];
CPUTLBEntry tlb_write[2][CPU_TLB_SIZE];
......@@ -358,7 +372,7 @@ int cpu_x86_inl(CPUX86State *env, int addr);
CPUX86State *cpu_x86_init(void);
int cpu_x86_exec(CPUX86State *s);
void cpu_x86_close(CPUX86State *s);
int cpu_x86_get_pic_interrupt(CPUX86State *s);
int cpu_get_pic_interrupt(CPUX86State *s);
/* this function must always be used to load data in the segment
cache: it synchronizes the hflags with the segment cache values */
......
......@@ -1189,6 +1189,8 @@ static inline int gen_intermediate_code_internal(CPUState *env,
return -1;
if (!(flags & HF_SS32_MASK))
return -1;
if (tb->cflags & CF_SINGLE_INSN)
return -1;
gen_code_end = gen_code_ptr +
GEN_CODE_MAX_SIZE - GEN_CODE_MAX_INSN_SIZE;
dc->gen_code_ptr = gen_code_ptr;
......
......@@ -4491,7 +4491,7 @@ static inline int gen_intermediate_code_internal(CPUState *env,
DisasContext dc1, *dc = &dc1;
uint8_t *pc_ptr;
uint16_t *gen_opc_end;
int flags, j, lj;
int flags, j, lj, cflags;
uint8_t *pc_start;
uint8_t *cs_base;
......@@ -4499,6 +4499,7 @@ static inline int gen_intermediate_code_internal(CPUState *env,
pc_start = (uint8_t *)tb->pc;
cs_base = (uint8_t *)tb->cs_base;
flags = tb->flags;
cflags = tb->cflags;
dc->pe = (flags >> HF_PE_SHIFT) & 1;
dc->code32 = (flags >> HF_CS32_SHIFT) & 1;
......@@ -4573,7 +4574,8 @@ static inline int gen_intermediate_code_internal(CPUState *env,
the flag and abort the translation to give the irqs a
change to be happen */
if (dc->tf || dc->singlestep_enabled ||
(flags & HF_INHIBIT_IRQ_MASK)) {
(flags & HF_INHIBIT_IRQ_MASK) ||
(cflags & CF_SINGLE_INSN)) {
gen_op_jmp_im(pc_ptr - dc->cs_base);
gen_eob(dc);
break;
......
......@@ -164,6 +164,13 @@ typedef struct CPUPPCState {
int user_mode_only; /* user mode only simulation */
struct TranslationBlock *current_tb; /* currently executing TB */
/* soft mmu support */
/* in order to avoid passing too many arguments to the memory
write helpers, we store some rarely used information in the CPU
context) */
unsigned long mem_write_pc; /* host pc at which the memory was
written */
unsigned long mem_write_vaddr; /* target virtual addr at which the
memory was written */
/* 0 = kernel, 1 = user (may have 2 = kernel code, 3 = user code ?) */
CPUTLBEntry tlb_read[2][CPU_TLB_SIZE];
CPUTLBEntry tlb_write[2][CPU_TLB_SIZE];
......
......@@ -43,6 +43,14 @@ typedef struct CPUSPARCState {
void *opaque;
/* NOTE: we allow 8 more registers to handle wrapping */
uint32_t regbase[NWINDOWS * 16 + 8];
/* in order to avoid passing too many arguments to the memory
write helpers, we store some rarely used information in the CPU
context) */
unsigned long mem_write_pc; /* host pc at which the memory was
written */
unsigned long mem_write_vaddr; /* target virtual addr at which the
memory was written */
} CPUSPARCState;
CPUSPARCState *cpu_sparc_init(void);
......
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