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Xing Lin
qemu
Commits
d537cf6c
Commit
d537cf6c
authored
Apr 07, 2007
by
pbrook
Browse files
Unify IRQ handling.
git-svn-id:
svn://svn.savannah.nongnu.org/qemu/trunk@2635
c046a42c-6fe2-441c-8c8c-71466251a162
parent
b6e27ab8
Changes
71
Hide whitespace changes
Inline
Side-by-side
Makefile.target
View file @
d537cf6c
...
...
@@ -360,6 +360,7 @@ VL_OBJS=vl.o osdep.o readline.o monitor.o pci.o console.o loader.o isa_mmio.o
VL_OBJS
+=
cutils.o
VL_OBJS
+=
block.o block-raw.o
VL_OBJS
+=
block-cow.o block-qcow.o aes.o block-vmdk.o block-cloop.o block-dmg.o block-bochs.o block-vpc.o block-vvfat.o block-qcow2.o
VL_OBJS
+=
irq.o
ifdef
CONFIG_WIN32
VL_OBJS
+=
tap-win32.o
endif
...
...
hw/acpi.c
View file @
d537cf6c
...
...
@@ -92,7 +92,7 @@ static void pm_update_sci(PIIX4PMState *s)
pmsts
=
get_pmsts
(
s
);
sci_level
=
(((
pmsts
&
s
->
pmen
)
&
(
RTC_EN
|
PWRBTN_EN
|
GBL_EN
|
TMROF_EN
))
!=
0
);
pci
_set_irq
(
&
s
->
dev
,
0
,
sci_level
);
qemu
_set_irq
(
s
->
dev
.
irq
[
0
]
,
sci_level
);
/* schedule a timer interruption if needed */
if
((
s
->
pmen
&
TMROF_EN
)
&&
!
(
pmsts
&
TMROF_EN
))
{
expire_time
=
muldiv64
(
s
->
tmr_overflow_time
,
ticks_per_sec
,
PM_FREQ
);
...
...
hw/adlib.c
View file @
d537cf6c
...
...
@@ -267,7 +267,7 @@ static void Adlib_fini (AdlibState *s)
AUD_remove_card
(
&
s
->
card
);
}
int
Adlib_init
(
AudioState
*
audio
)
int
Adlib_init
(
AudioState
*
audio
,
qemu_irq
*
pic
)
{
AdlibState
*
s
=
&
glob_adlib
;
audsettings_t
as
;
...
...
hw/apb_pci.c
View file @
d537cf6c
...
...
@@ -200,14 +200,14 @@ static int pci_pbm_map_irq(PCIDevice *pci_dev, int irq_num)
return
bus_offset
+
irq_num
;
}
static
void
pci_apb_set_irq
(
void
*
pic
,
int
irq_num
,
int
level
)
static
void
pci_apb_set_irq
(
qemu_irq
*
pic
,
int
irq_num
,
int
level
)
{
/* PCI IRQ map onto the first 32 INO. */
pic
_set_irq
_new
(
pic
,
irq_num
,
level
);
qemu
_set_irq
(
pic
[
irq_num
]
,
level
);
}
PCIBus
*
pci_apb_init
(
target_ulong
special_base
,
target_ulong
mem_base
,
void
*
pic
)
qemu_irq
*
pic
)
{
APBState
*
s
;
PCIDevice
*
d
;
...
...
hw/arm_gic.c
View file @
d537cf6c
...
...
@@ -60,10 +60,8 @@ typedef struct gic_irq_state
typedef
struct
gic_state
{
arm_pic_handler
handler
;
uint32_t
base
;
void
*
parent
;
int
parent_irq
;
qemu_irq
parent_irq
;
int
enabled
;
int
cpu_enabled
;
...
...
@@ -88,7 +86,7 @@ static void gic_update(gic_state *s)
s
->
current_pending
=
1023
;
if
(
!
s
->
enabled
||
!
s
->
cpu_enabled
)
{
pic_set_irq_new
(
s
->
parent
,
s
->
parent_irq
,
0
);
qemu_irq_lower
(
s
->
parent_irq
);
return
;
}
best_prio
=
0x100
;
...
...
@@ -102,12 +100,12 @@ static void gic_update(gic_state *s)
}
}
if
(
best_prio
>
s
->
priority_mask
)
{
pic_set_irq_new
(
s
->
parent
,
s
->
parent_irq
,
0
);
qemu_irq_lower
(
s
->
parent_irq
);
}
else
{
s
->
current_pending
=
best_irq
;
if
(
best_prio
<
s
->
running_priority
)
{
DPRINTF
(
"Raised pending IRQ %d
\n
"
,
best_irq
);
pic_set_irq_new
(
s
->
parent
,
s
->
parent_irq
,
1
);
qemu_irq_raise
(
s
->
parent_irq
);
}
}
}
...
...
@@ -150,7 +148,7 @@ static uint32_t gic_acknowledge_irq(gic_state *s)
DPRINTF
(
"ACK no pending IRQ
\n
"
);
return
1023
;
}
pic_set_irq_new
(
s
->
parent
,
s
->
parent_irq
,
0
);
qemu_irq_lower
(
s
->
parent_irq
);
s
->
last_active
[
new_irq
]
=
s
->
running_irq
;
/* For level triggered interrupts we clear the pending bit while
the interrupt is active. */
...
...
@@ -520,16 +518,16 @@ static void gic_reset(gic_state *s)
s
->
cpu_enabled
=
0
;
}
void
*
arm_gic_init
(
uint32_t
base
,
void
*
parent
,
int
parent_irq
)
qemu_irq
*
arm_gic_init
(
uint32_t
base
,
qemu_irq
parent_irq
)
{
gic_state
*
s
;
qemu_irq
*
qi
;
int
iomemtype
;
s
=
(
gic_state
*
)
qemu_mallocz
(
sizeof
(
gic_state
));
if
(
!
s
)
return
NULL
;
s
->
handler
=
gic_set_irq
;
s
->
parent
=
parent
;
qi
=
qemu_allocate_irqs
(
gic_set_irq
,
s
,
GIC_NIRQ
);
s
->
parent_irq
=
parent_irq
;
if
(
base
!=
0xffffffff
)
{
iomemtype
=
cpu_register_io_memory
(
0
,
gic_cpu_readfn
,
...
...
@@ -543,5 +541,5 @@ void *arm_gic_init(uint32_t base, void *parent, int parent_irq)
s
->
base
=
0
;
}
gic_reset
(
s
);
return
s
;
return
qi
;
}
hw/arm_pic.c
View file @
d537cf6c
...
...
@@ -11,11 +11,6 @@
#include "arm_pic.h"
/* Stub functions for hardware that doesn't exist. */
void
pic_set_irq
(
int
irq
,
int
level
)
{
cpu_abort
(
cpu_single_env
,
"pic_set_irq"
);
}
void
pic_info
(
void
)
{
}
...
...
@@ -25,49 +20,29 @@ void irq_info(void)
}
void
pic_set_irq_new
(
void
*
opaque
,
int
irq
,
int
level
)
{
arm_pic_handler
*
p
=
(
arm_pic_handler
*
)
opaque
;
/* Call the real handler. */
(
*
p
)(
opaque
,
irq
,
level
);
}
/* Model the IRQ/FIQ CPU interrupt lines as a two input interrupt controller.
Input 0 is IRQ and input 1 is FIQ. */
typedef
struct
{
arm_pic_handler
handler
;
CPUState
*
cpu_env
;
}
arm_pic_cpu_state
;
/* Input 0 is IRQ and input 1 is FIQ. */
static
void
arm_pic_cpu_handler
(
void
*
opaque
,
int
irq
,
int
level
)
{
arm_pic_cpu_s
tate
*
s
=
(
arm_pic_cpu_s
tate
*
)
opaque
;
CPUS
tate
*
env
=
(
CPUS
tate
*
)
opaque
;
switch
(
irq
)
{
case
ARM_PIC_CPU_IRQ
:
if
(
level
)
cpu_interrupt
(
s
->
cpu_
env
,
CPU_INTERRUPT_HARD
);
cpu_interrupt
(
env
,
CPU_INTERRUPT_HARD
);
else
cpu_reset_interrupt
(
s
->
cpu_
env
,
CPU_INTERRUPT_HARD
);
cpu_reset_interrupt
(
env
,
CPU_INTERRUPT_HARD
);
break
;
case
ARM_PIC_CPU_FIQ
:
if
(
level
)
cpu_interrupt
(
s
->
cpu_
env
,
CPU_INTERRUPT_FIQ
);
cpu_interrupt
(
env
,
CPU_INTERRUPT_FIQ
);
else
cpu_reset_interrupt
(
s
->
cpu_
env
,
CPU_INTERRUPT_FIQ
);
cpu_reset_interrupt
(
env
,
CPU_INTERRUPT_FIQ
);
break
;
default:
cpu_abort
(
s
->
cpu_env
,
"arm_pic_cpu_handler: Bad interrput line %d
\n
"
,
irq
);
cpu_abort
(
env
,
"arm_pic_cpu_handler: Bad interrput line %d
\n
"
,
irq
);
}
}
void
*
arm_pic_init_cpu
(
CPUState
*
env
)
qemu_irq
*
arm_pic_init_cpu
(
CPUState
*
env
)
{
arm_pic_cpu_state
*
s
;
s
=
(
arm_pic_cpu_state
*
)
malloc
(
sizeof
(
arm_pic_cpu_state
));
s
->
handler
=
arm_pic_cpu_handler
;
s
->
cpu_env
=
env
;
return
s
;
return
qemu_allocate_irqs
(
arm_pic_cpu_handler
,
env
,
2
);
}
hw/arm_pic.h
View file @
d537cf6c
...
...
@@ -14,14 +14,10 @@
#ifndef ARM_INTERRUPT_H
#define ARM_INTERRUPT_H 1
/* The first element of an individual PIC state structures should
be a pointer to the handler routine. */
typedef
void
(
*
arm_pic_handler
)(
void
*
opaque
,
int
irq
,
int
level
);
/* The CPU is also modeled as an interrupt controller. */
#define ARM_PIC_CPU_IRQ 0
#define ARM_PIC_CPU_FIQ 1
void
*
arm_pic_init_cpu
(
CPUState
*
env
);
qemu_irq
*
arm_pic_init_cpu
(
CPUState
*
env
);
#endif
/* !ARM_INTERRUPT_H */
hw/arm_timer.c
View file @
d537cf6c
...
...
@@ -32,8 +32,7 @@ typedef struct {
int
raw_freq
;
int
freq
;
int
int_level
;
void
*
pic
;
int
irq
;
qemu_irq
irq
;
}
arm_timer_state
;
/* Calculate the new expiry time of the given timer. */
...
...
@@ -85,9 +84,9 @@ static void arm_timer_update(arm_timer_state *s, int64_t now)
}
/* Update interrupts. */
if
(
s
->
int_level
&&
(
s
->
control
&
TIMER_CTRL_IE
))
{
pic_set_irq_new
(
s
->
pic
,
s
->
irq
,
1
);
qemu_irq_raise
(
s
->
irq
);
}
else
{
pic_set_irq_new
(
s
->
pic
,
s
->
irq
,
0
);
qemu_irq_lower
(
s
->
irq
);
}
next
=
now
;
...
...
@@ -215,12 +214,11 @@ static void arm_timer_tick(void *opaque)
arm_timer_update
((
arm_timer_state
*
)
opaque
,
now
);
}
static
void
*
arm_timer_init
(
uint32_t
freq
,
void
*
pic
,
int
irq
)
static
void
*
arm_timer_init
(
uint32_t
freq
,
qemu_irq
irq
)
{
arm_timer_state
*
s
;
s
=
(
arm_timer_state
*
)
qemu_mallocz
(
sizeof
(
arm_timer_state
));
s
->
pic
=
pic
;
s
->
irq
=
irq
;
s
->
raw_freq
=
s
->
freq
=
1000000
;
s
->
control
=
TIMER_CTRL_IE
;
...
...
@@ -237,22 +235,19 @@ static void *arm_timer_init(uint32_t freq, void *pic, int irq)
Integrator/CP timer modules. */
typedef
struct
{
/* Include a pseudo-PIC device to merge the two interrupt sources. */
arm_pic_handler
handler
;
void
*
timer
[
2
];
int
level
[
2
];
uint32_t
base
;
/* The output PIC device. */
void
*
pic
;
int
irq
;
qemu_irq
irq
;
}
sp804_state
;
/* Merge the IRQs from the two component devices. */
static
void
sp804_set_irq
(
void
*
opaque
,
int
irq
,
int
level
)
{
sp804_state
*
s
=
(
sp804_state
*
)
opaque
;
s
->
level
[
irq
]
=
level
;
pic
_set_irq
_new
(
s
->
pic
,
s
->
irq
,
s
->
level
[
0
]
||
s
->
level
[
1
]);
qemu
_set_irq
(
s
->
irq
,
s
->
level
[
0
]
||
s
->
level
[
1
]);
}
static
uint32_t
sp804_read
(
void
*
opaque
,
target_phys_addr_t
offset
)
...
...
@@ -293,20 +288,20 @@ static CPUWriteMemoryFunc *sp804_writefn[] = {
sp804_write
};
void
sp804_init
(
uint32_t
base
,
void
*
pic
,
int
irq
)
void
sp804_init
(
uint32_t
base
,
qemu_irq
irq
)
{
int
iomemtype
;
sp804_state
*
s
;
qemu_irq
*
qi
;
s
=
(
sp804_state
*
)
qemu_mallocz
(
sizeof
(
sp804_state
));
s
->
handler
=
sp804_set_irq
;
qi
=
qemu_allocate_irqs
(
sp804_set_irq
,
s
,
2
)
;
s
->
base
=
base
;
s
->
pic
=
pic
;
s
->
irq
=
irq
;
/* ??? The timers are actually configurable between 32kHz and 1MHz, but
we don't implement that. */
s
->
timer
[
0
]
=
arm_timer_init
(
1000000
,
s
,
0
);
s
->
timer
[
1
]
=
arm_timer_init
(
1000000
,
s
,
1
);
s
->
timer
[
0
]
=
arm_timer_init
(
1000000
,
qi
[
0
]
);
s
->
timer
[
1
]
=
arm_timer_init
(
1000000
,
qi
[
1
]
);
iomemtype
=
cpu_register_io_memory
(
0
,
sp804_readfn
,
sp804_writefn
,
s
);
cpu_register_physical_memory
(
base
,
0x00000fff
,
iomemtype
);
...
...
@@ -362,7 +357,7 @@ static CPUWriteMemoryFunc *icp_pit_writefn[] = {
icp_pit_write
};
void
icp_pit_init
(
uint32_t
base
,
void
*
pic
,
int
irq
)
void
icp_pit_init
(
uint32_t
base
,
qemu_irq
*
pic
,
int
irq
)
{
int
iomemtype
;
icp_pit_state
*
s
;
...
...
@@ -370,10 +365,10 @@ void icp_pit_init(uint32_t base, void *pic, int irq)
s
=
(
icp_pit_state
*
)
qemu_mallocz
(
sizeof
(
icp_pit_state
));
s
->
base
=
base
;
/* Timer 0 runs at the system clock speed (40MHz). */
s
->
timer
[
0
]
=
arm_timer_init
(
40000000
,
pic
,
irq
);
s
->
timer
[
0
]
=
arm_timer_init
(
40000000
,
pic
[
irq
]
);
/* The other two timers run at 1MHz. */
s
->
timer
[
1
]
=
arm_timer_init
(
1000000
,
pic
,
irq
+
1
);
s
->
timer
[
2
]
=
arm_timer_init
(
1000000
,
pic
,
irq
+
2
);
s
->
timer
[
1
]
=
arm_timer_init
(
1000000
,
pic
[
irq
+
1
]
);
s
->
timer
[
2
]
=
arm_timer_init
(
1000000
,
pic
[
irq
+
2
]
);
iomemtype
=
cpu_register_io_memory
(
0
,
icp_pit_readfn
,
icp_pit_writefn
,
s
);
...
...
hw/cs4231.c
View file @
d537cf6c
...
...
@@ -47,9 +47,6 @@ typedef struct CSState {
#ifdef DEBUG_CS
#define DPRINTF(fmt, args...) \
do { printf("CS: " fmt , ##args); } while (0)
#define pic_set_irq_new(intctl, irq, level) \
do { printf("CS: set_irq(%d): %d\n", (irq), (level)); \
pic_set_irq_new((intctl), (irq),(level));} while (0)
#else
#define DPRINTF(fmt, args...)
#endif
...
...
hw/cuda.c
View file @
d537cf6c
...
...
@@ -124,9 +124,7 @@ typedef struct CUDAState {
int
data_in_index
;
int
data_out_index
;
SetIRQFunc
*
set_irq
;
int
irq
;
void
*
irq_opaque
;
qemu_irq
irq
;
uint8_t
autopoll
;
uint8_t
data_in
[
128
];
uint8_t
data_out
[
16
];
...
...
@@ -145,9 +143,9 @@ static void cuda_timer_update(CUDAState *s, CUDATimer *ti,
static
void
cuda_update_irq
(
CUDAState
*
s
)
{
if
(
s
->
ifr
&
s
->
ier
&
(
SR_INT
|
T1_INT
))
{
s
->
set_irq
(
s
->
irq_opaque
,
s
->
irq
,
1
);
qemu_irq_raise
(
s
->
irq
);
}
else
{
s
->
set_irq
(
s
->
irq_opaque
,
s
->
irq
,
0
);
qemu_irq_lower
(
s
->
irq
);
}
}
...
...
@@ -630,13 +628,11 @@ static CPUReadMemoryFunc *cuda_read[] = {
&
cuda_readl
,
};
int
cuda_init
(
SetIRQFunc
*
set_irq
,
void
*
irq_opaque
,
int
irq
)
int
cuda_init
(
qemu_irq
irq
)
{
CUDAState
*
s
=
&
cuda_state
;
int
cuda_mem_index
;
s
->
set_irq
=
set_irq
;
s
->
irq_opaque
=
irq_opaque
;
s
->
irq
=
irq
;
s
->
timers
[
0
].
index
=
0
;
...
...
hw/eepro100.c
View file @
d537cf6c
...
...
@@ -326,7 +326,7 @@ static void disable_interrupt(EEPRO100State * s)
{
if
(
s
->
int_stat
)
{
logout
(
"interrupt disabled
\n
"
);
pci_set_irq
(
s
->
pci_dev
,
0
,
0
);
qemu_irq_lower
(
s
->
pci_dev
->
irq
[
0
]
);
s
->
int_stat
=
0
;
}
}
...
...
@@ -335,7 +335,7 @@ static void enable_interrupt(EEPRO100State * s)
{
if
(
!
s
->
int_stat
)
{
logout
(
"interrupt enabled
\n
"
);
pci_set_irq
(
s
->
pci_dev
,
0
,
1
);
qemu_irq_raise
(
s
->
pci_dev
->
irq
[
0
]
);
s
->
int_stat
=
1
;
}
}
...
...
hw/es1370.c
View file @
d537cf6c
...
...
@@ -324,7 +324,7 @@ static void es1370_update_status (ES1370State *s, uint32_t new_status)
else
{
s
->
status
=
new_status
&
~
STAT_INTR
;
}
pci
_set_irq
(
s
->
pci_dev
,
0
,
!!
level
);
qemu
_set_irq
(
s
->
pci_dev
->
irq
[
0
]
,
!!
level
);
}
static
void
es1370_reset
(
ES1370State
*
s
)
...
...
@@ -350,7 +350,7 @@ static void es1370_reset (ES1370State *s)
s
->
dac_voice
[
i
]
=
NULL
;
}
}
pci_set_irq
(
s
->
pci_dev
,
0
,
0
);
qemu_irq_lower
(
s
->
pci_dev
->
irq
[
0
]
);
}
static
void
es1370_maybe_lower_irq
(
ES1370State
*
s
,
uint32_t
sctl
)
...
...
hw/fdc.c
View file @
d537cf6c
...
...
@@ -368,7 +368,7 @@ struct fdctrl_t {
/* Controller's identification */
uint8_t
version
;
/* HW */
int
irq_lvl
;
qemu_irq
irq
;
int
dma_chann
;
uint32_t
io_base
;
/* Controller state */
...
...
@@ -485,7 +485,7 @@ static CPUWriteMemoryFunc *fdctrl_mem_write[3] = {
fdctrl_write_mem
,
};
fdctrl_t
*
fdctrl_init
(
int
irq_lvl
,
int
dma_chann
,
int
mem_mapped
,
fdctrl_t
*
fdctrl_init
(
qemu_irq
irq
,
int
dma_chann
,
int
mem_mapped
,
uint32_t
io_base
,
BlockDriverState
**
fds
)
{
...
...
@@ -501,7 +501,7 @@ fdctrl_t *fdctrl_init (int irq_lvl, int dma_chann, int mem_mapped,
fdctrl_result_timer
,
fdctrl
);
fdctrl
->
version
=
0x90
;
/* Intel 82078 controller */
fdctrl
->
irq
_lvl
=
irq
_lvl
;
fdctrl
->
irq
=
irq
;
fdctrl
->
dma_chann
=
dma_chann
;
fdctrl
->
io_base
=
io_base
;
fdctrl
->
config
=
0x60
;
/* Implicit seek, polling & FIFO enabled */
...
...
@@ -542,7 +542,7 @@ int fdctrl_get_drive_type(fdctrl_t *fdctrl, int drive_num)
static
void
fdctrl_reset_irq
(
fdctrl_t
*
fdctrl
)
{
FLOPPY_DPRINTF
(
"Reset interrupt
\n
"
);
pic
_set_irq
(
fdctrl
->
irq
_lvl
,
0
);
qemu
_set_irq
(
fdctrl
->
irq
,
0
);
fdctrl
->
state
&=
~
FD_CTRL_INTR
;
}
...
...
@@ -557,7 +557,7 @@ static void fdctrl_raise_irq (fdctrl_t *fdctrl, uint8_t status)
}
#endif
if
(
~
(
fdctrl
->
state
&
FD_CTRL_INTR
))
{
pic
_set_irq
(
fdctrl
->
irq
_lvl
,
1
);
qemu
_set_irq
(
fdctrl
->
irq
,
1
);
fdctrl
->
state
|=
FD_CTRL_INTR
;
}
FLOPPY_DPRINTF
(
"Set interrupt status to 0x%02x
\n
"
,
status
);
...
...
hw/grackle_pci.c
View file @
d537cf6c
...
...
@@ -80,12 +80,12 @@ static int pci_grackle_map_irq(PCIDevice *pci_dev, int irq_num)
return
(
irq_num
+
(
pci_dev
->
devfn
>>
3
))
&
3
;
}
static
void
pci_grackle_set_irq
(
void
*
pic
,
int
irq_num
,
int
level
)
static
void
pci_grackle_set_irq
(
qemu_irq
*
pic
,
int
irq_num
,
int
level
)
{
heathrow_pic
_set_irq
(
pic
,
irq_num
+
8
,
level
);
qemu
_set_irq
(
pic
[
irq_num
+
8
]
,
level
);
}
PCIBus
*
pci_grackle_init
(
uint32_t
base
,
void
*
pic
)
PCIBus
*
pci_grackle_init
(
uint32_t
base
,
qemu_irq
*
pic
)
{
GrackleState
*
s
;
PCIDevice
*
d
;
...
...
hw/gt64xxx.c
View file @
d537cf6c
...
...
@@ -520,7 +520,7 @@ static int pci_gt64120_map_irq(PCIDevice *pci_dev, int irq_num)
extern
PCIDevice
*
piix4_dev
;
static
int
pci_irq_levels
[
4
];
static
void
pci_gt64120_set_irq
(
void
*
pic
,
int
irq_num
,
int
level
)
static
void
pci_gt64120_set_irq
(
qemu_irq
*
pic
,
int
irq_num
,
int
level
)
{
int
i
,
pic_irq
,
pic_level
;
...
...
@@ -537,7 +537,7 @@ static void pci_gt64120_set_irq(void *pic, int irq_num, int level)
if
(
pic_irq
==
piix4_dev
->
config
[
0x60
+
i
])
pic_level
|=
pci_irq_levels
[
i
];
}
pic
_set_irq
(
pic_irq
,
pic_level
);
qemu
_set_irq
(
pic
[
pic
_irq
]
,
pic_level
);
}
}
...
...
@@ -608,7 +608,7 @@ void gt64120_reset(void *opaque)
gt64120_pci_mapping
(
s
);
}
PCIBus
*
pci_gt64120_init
(
void
*
pic
)
PCIBus
*
pci_gt64120_init
(
qemu_irq
*
pic
)
{
GT64120State
*
s
;
PCIDevice
*
d
;
...
...
hw/heathrow_pic.c
View file @
d537cf6c
...
...
@@ -32,9 +32,9 @@ typedef struct HeathrowPIC {
uint32_t
level_triggered
;
}
HeathrowPIC
;
struct
HeathrowPICS
{
typedef
struct
HeathrowPICS
{
HeathrowPIC
pics
[
2
];
};
}
HeathrowPICS
;
static
inline
int
check_irq
(
HeathrowPIC
*
pic
)
{
...
...
@@ -130,7 +130,7 @@ static CPUReadMemoryFunc *pic_read[] = {
};
void
heathrow_pic_set_irq
(
void
*
opaque
,
int
num
,
int
level
)
static
void
heathrow_pic_set_irq
(
void
*
opaque
,
int
num
,
int
level
)
{
HeathrowPICS
*
s
=
opaque
;
HeathrowPIC
*
pic
;
...
...
@@ -156,7 +156,7 @@ void heathrow_pic_set_irq(void *opaque, int num, int level)
heathrow_pic_update
(
s
);
}
HeathrowPICS
*
heathrow_pic_init
(
int
*
pmem_index
)
qemu_irq
*
heathrow_pic_init
(
int
*
pmem_index
)
{
HeathrowPICS
*
s
;
...
...
@@ -164,5 +164,5 @@ HeathrowPICS *heathrow_pic_init(int *pmem_index)
s
->
pics
[
0
].
level_triggered
=
0
;
s
->
pics
[
1
].
level_triggered
=
0x1ff00000
;
*
pmem_index
=
cpu_register_io_memory
(
0
,
pic_read
,
pic_write
,
s
);
return
s
;
return
qemu_allocate_irqs
(
heathrow_pic_set_irq
,
s
,
64
)
;
}
hw/i8254.c
View file @
d537cf6c
...
...
@@ -47,7 +47,7 @@ typedef struct PITChannelState {
/* irq handling */
int64_t
next_transition_time
;
QEMUTimer
*
irq_timer
;
int
irq
;
qemu_irq
irq
;
}
PITChannelState
;
struct
PITState
{
...
...
@@ -366,7 +366,7 @@ static void pit_irq_timer_update(PITChannelState *s, int64_t current_time)
return
;
expire_time
=
pit_get_next_transition_time
(
s
,
current_time
);
irq_level
=
pit_get_out1
(
s
,
current_time
);
pic
_set_irq
(
s
->
irq
,
irq_level
);
qemu
_set_irq
(
s
->
irq
,
irq_level
);
#ifdef DEBUG_PIT
printf
(
"irq_level=%d next_delay=%f
\n
"
,
irq_level
,
...
...
@@ -460,7 +460,7 @@ static void pit_reset(void *opaque)
}
}
PITState
*
pit_init
(
int
base
,
int
irq
)
PITState
*
pit_init
(
int
base
,
qemu_irq
irq
)
{
PITState
*
pit
=
&
pit_state
;
PITChannelState
*
s
;
...
...
hw/i8259.c
View file @
d537cf6c
...
...
@@ -54,7 +54,7 @@ struct PicState2 {
/* 0 is master pic, 1 is slave pic */
/* XXX: better separation between the two pics */
PicState
pics
[
2
];
IRQRequestFunc
*
irq_request
;
qemu_irq
parent_irq
;
void
*
irq_request_opaque
;
/* IOAPIC callback support */
SetIRQFunc
*
alt_irq_func
;
...
...
@@ -160,13 +160,13 @@ void pic_update_irq(PicState2 *s)
}
printf
(
"pic: cpu_interrupt
\n
"
);
#endif
s
->
irq_request
(
s
->
irq_request_opaque
,
1
);
qemu_irq_raise
(
s
->
parent_irq
);
}
/* all targets should do this rather than acking the IRQ in the cpu */
#if defined(TARGET_MIPS)
else
{
s
->
irq_request
(
s
->
irq_request_opaque
,
0
);
qemu_irq_lower
(
s
->
parent_irq
);
}
#endif
}
...
...
@@ -175,14 +175,14 @@ void pic_update_irq(PicState2 *s)
int64_t
irq_time
[
16
];
#endif
void
pic
_set_irq
_new
(
void
*
opaque
,
int
irq
,
int
level
)
void
i8259
_set_irq
(
void
*
opaque
,
int
irq
,
int
level
)
{
PicState2
*
s
=
opaque
;
#if defined(DEBUG_PIC) || defined(DEBUG_IRQ_COUNT)
if
(
level
!=
irq_level
[
irq
])
{
#if defined(DEBUG_PIC)
printf
(
"
pic
_set_irq: irq=%d level=%d
\n
"
,
irq
,
level
);
printf
(
"
i8259
_set_irq: irq=%d level=%d
\n
"
,
irq
,
level
);
#endif
irq_level
[
irq
]
=
level
;
#ifdef DEBUG_IRQ_COUNT
...
...
@@ -203,12 +203,6 @@ void pic_set_irq_new(void *opaque, int irq, int level)
pic_update_irq
(
s
);
}
/* obsolete function */
void
pic_set_irq
(
int
irq
,
int
level
)
{
pic_set_irq_new
(
isa_pic
,
irq
,
level
);
}
/* acknowledge interrupt 'irq' */
static
inline
void
pic_intack
(
PicState
*
s
,
int
irq
)
{
...
...
@@ -297,7 +291,7 @@ static void pic_ioport_write(void *opaque, uint32_t addr, uint32_t val)
/* init */
pic_reset
(
s
);
/* deassert a pending interrupt */
s
->
pics_state
->
irq_request
(
s
->
pics_state
->
irq_request_opaque
,
0
);
qemu_irq_lower
(
s
->
pics_state
->
parent_irq
);
s
->
init_state
=
1
;
s
->
init4
=
val
&
1
;
s
->
single_mode
=
val
&
2
;
...
...
@@ -546,9 +540,10 @@ void irq_info(void)
#endif
}
PicState2
*
pic_init
(
IRQRequestFunc
*
irq_request
,
void
*
irq_request_opaque
)
qemu_irq
*
i8259_init
(
qemu_irq
parent_irq
)
{
PicState2
*
s
;
s
=
qemu_mallocz
(
sizeof
(
PicState2
));
if
(
!
s
)
return
NULL
;
...
...
@@ -556,11 +551,11 @@ PicState2 *pic_init(IRQRequestFunc *