Commit d0f2c4c6 authored by malc's avatar malc

Do not use dprintf

dprintf is already claimed by POSIX[1], and on at least one system
is implemented as a macro

[1] http://www.opengroup.org/onlinepubs/9699919799/functions/dprintf.htmlSigned-off-by: default avatarmalc <av1474@comtv.ru>
parent bc4347b8
......@@ -33,10 +33,10 @@
//#define DEBUG_BLK_MIGRATION
#ifdef DEBUG_BLK_MIGRATION
#define dprintf(fmt, ...) \
#define DPRINTF(fmt, ...) \
do { printf("blk_migration: " fmt, ## __VA_ARGS__); } while (0)
#else
#define dprintf(fmt, ...) \
#define DPRINTF(fmt, ...) \
do { } while (0)
#endif
......@@ -332,7 +332,7 @@ static void flush_blks(QEMUFile* f)
{
BlkMigBlock *blk;
dprintf("%s Enter submitted %d read_done %d transferred %d\n",
DPRINTF("%s Enter submitted %d read_done %d transferred %d\n",
__FUNCTION__, block_mig_state.submitted, block_mig_state.read_done,
block_mig_state.transferred);
......@@ -355,7 +355,7 @@ static void flush_blks(QEMUFile* f)
assert(block_mig_state.read_done >= 0);
}
dprintf("%s Exit submitted %d read_done %d transferred %d\n", __FUNCTION__,
DPRINTF("%s Exit submitted %d read_done %d transferred %d\n", __FUNCTION__,
block_mig_state.submitted, block_mig_state.read_done,
block_mig_state.transferred);
}
......@@ -400,7 +400,7 @@ static void blk_mig_cleanup(Monitor *mon)
static int block_save_live(Monitor *mon, QEMUFile *f, int stage, void *opaque)
{
dprintf("Enter save live stage %d submitted %d transferred %d\n",
DPRINTF("Enter save live stage %d submitted %d transferred %d\n",
stage, block_mig_state.submitted, block_mig_state.transferred);
if (stage < 0) {
......
......@@ -29,9 +29,9 @@
// #define DEBUG_VERBOSE
#ifdef DEBUG_CURL
#define dprintf(fmt, ...) do { printf(fmt, ## __VA_ARGS__); } while (0)
#define DPRINTF(fmt, ...) do { printf(fmt, ## __VA_ARGS__); } while (0)
#else
#define dprintf(fmt, ...) do { } while (0)
#define DPRINTF(fmt, ...) do { } while (0)
#endif
#define CURL_NUM_STATES 8
......@@ -80,7 +80,7 @@ static void curl_multi_do(void *arg);
static int curl_sock_cb(CURL *curl, curl_socket_t fd, int action,
void *s, void *sp)
{
dprintf("CURL (AIO): Sock action %d on fd %d\n", action, fd);
DPRINTF("CURL (AIO): Sock action %d on fd %d\n", action, fd);
switch (action) {
case CURL_POLL_IN:
qemu_aio_set_fd_handler(fd, curl_multi_do, NULL, NULL, NULL, s);
......@@ -118,7 +118,7 @@ static size_t curl_read_cb(void *ptr, size_t size, size_t nmemb, void *opaque)
size_t realsize = size * nmemb;
int i;
dprintf("CURL: Just reading %lld bytes\n", (unsigned long long)realsize);
DPRINTF("CURL: Just reading %lld bytes\n", (unsigned long long)realsize);
if (!s || !s->orig_buf)
goto read_end;
......@@ -349,7 +349,7 @@ static int curl_open(BlockDriverState *bs, const char *filename, int flags)
inited = 1;
}
dprintf("CURL: Opening %s\n", file);
DPRINTF("CURL: Opening %s\n", file);
s->url = file;
state = curl_init_state(s);
if (!state)
......@@ -368,7 +368,7 @@ static int curl_open(BlockDriverState *bs, const char *filename, int flags)
s->len = (size_t)d;
else if(!s->len)
goto out;
dprintf("CURL: Size = %lld\n", (long long)s->len);
DPRINTF("CURL: Size = %lld\n", (long long)s->len);
curl_clean_state(state);
curl_easy_cleanup(state->curl);
......@@ -451,7 +451,7 @@ static BlockDriverAIOCB *curl_aio_readv(BlockDriverState *bs,
state->acb[0] = acb;
snprintf(state->range, 127, "%lld-%lld", (long long)start, (long long)end);
dprintf("CURL (AIO): Reading %d at %lld (%s)\n", (nb_sectors * SECTOR_SIZE), start, state->range);
DPRINTF("CURL (AIO): Reading %d at %lld (%s)\n", (nb_sectors * SECTOR_SIZE), start, state->range);
curl_easy_setopt(state->curl, CURLOPT_RANGE, state->range);
curl_multi_add_handle(s->multi, state->curl);
......@@ -465,7 +465,7 @@ static void curl_close(BlockDriverState *bs)
BDRVCURLState *s = bs->opaque;
int i;
dprintf("CURL: Close\n");
DPRINTF("CURL: Close\n");
for (i=0; i<CURL_NUM_STATES; i++) {
if (s->states[i].in_use)
curl_clean_state(&s->states[i]);
......
......@@ -39,10 +39,10 @@ typedef struct QEMUFileBuffered
} QEMUFileBuffered;
#ifdef DEBUG_BUFFERED_FILE
#define dprintf(fmt, ...) \
#define DPRINTF(fmt, ...) \
do { printf("buffered-file: " fmt, ## __VA_ARGS__); } while (0)
#else
#define dprintf(fmt, ...) \
#define DPRINTF(fmt, ...) \
do { } while (0)
#endif
......@@ -52,7 +52,7 @@ static void buffered_append(QEMUFileBuffered *s,
if (size > (s->buffer_capacity - s->buffer_size)) {
void *tmp;
dprintf("increasing buffer capacity from %zu by %zu\n",
DPRINTF("increasing buffer capacity from %zu by %zu\n",
s->buffer_capacity, size + 1024);
s->buffer_capacity += size + 1024;
......@@ -75,11 +75,11 @@ static void buffered_flush(QEMUFileBuffered *s)
size_t offset = 0;
if (s->has_error) {
dprintf("flush when error, bailing\n");
DPRINTF("flush when error, bailing\n");
return;
}
dprintf("flushing %zu byte(s) of data\n", s->buffer_size);
DPRINTF("flushing %zu byte(s) of data\n", s->buffer_size);
while (offset < s->buffer_size) {
ssize_t ret;
......@@ -87,22 +87,22 @@ static void buffered_flush(QEMUFileBuffered *s)
ret = s->put_buffer(s->opaque, s->buffer + offset,
s->buffer_size - offset);
if (ret == -EAGAIN) {
dprintf("backend not ready, freezing\n");
DPRINTF("backend not ready, freezing\n");
s->freeze_output = 1;
break;
}
if (ret <= 0) {
dprintf("error flushing data, %zd\n", ret);
DPRINTF("error flushing data, %zd\n", ret);
s->has_error = 1;
break;
} else {
dprintf("flushed %zd byte(s)\n", ret);
DPRINTF("flushed %zd byte(s)\n", ret);
offset += ret;
}
}
dprintf("flushed %zu of %zu byte(s)\n", offset, s->buffer_size);
DPRINTF("flushed %zu of %zu byte(s)\n", offset, s->buffer_size);
memmove(s->buffer, s->buffer + offset, s->buffer_size - offset);
s->buffer_size -= offset;
}
......@@ -113,45 +113,45 @@ static int buffered_put_buffer(void *opaque, const uint8_t *buf, int64_t pos, in
int offset = 0;
ssize_t ret;
dprintf("putting %d bytes at %" PRId64 "\n", size, pos);
DPRINTF("putting %d bytes at %" PRId64 "\n", size, pos);
if (s->has_error) {
dprintf("flush when error, bailing\n");
DPRINTF("flush when error, bailing\n");
return -EINVAL;
}
dprintf("unfreezing output\n");
DPRINTF("unfreezing output\n");
s->freeze_output = 0;
buffered_flush(s);
while (!s->freeze_output && offset < size) {
if (s->bytes_xfer > s->xfer_limit) {
dprintf("transfer limit exceeded when putting\n");
DPRINTF("transfer limit exceeded when putting\n");
break;
}
ret = s->put_buffer(s->opaque, buf + offset, size - offset);
if (ret == -EAGAIN) {
dprintf("backend not ready, freezing\n");
DPRINTF("backend not ready, freezing\n");
s->freeze_output = 1;
break;
}
if (ret <= 0) {
dprintf("error putting\n");
DPRINTF("error putting\n");
s->has_error = 1;
offset = -EINVAL;
break;
}
dprintf("put %zd byte(s)\n", ret);
DPRINTF("put %zd byte(s)\n", ret);
offset += ret;
s->bytes_xfer += ret;
}
if (offset >= 0) {
dprintf("buffering %d bytes\n", size - offset);
DPRINTF("buffering %d bytes\n", size - offset);
buffered_append(s, buf + offset, size - offset);
offset = size;
}
......@@ -164,7 +164,7 @@ static int buffered_close(void *opaque)
QEMUFileBuffered *s = opaque;
int ret;
dprintf("closing\n");
DPRINTF("closing\n");
while (!s->has_error && s->buffer_size) {
buffered_flush(s);
......
......@@ -31,9 +31,9 @@
//#define DEBUG
#ifdef DEBUG
#define dprintf(fmt, ...) fprintf(stderr, "%s: " fmt, __FUNCTION__, ##__VA_ARGS__)
#define DPRINTF(fmt, ...) fprintf(stderr, "%s: " fmt, __FUNCTION__, ##__VA_ARGS__)
#else
#define dprintf(fmt, ...)
#define DPRINTF(fmt, ...)
#endif
#define GT_REGS (0x1000 >> 2)
......@@ -276,7 +276,7 @@ static void gt64120_isd_mapping(GT64120State *s)
check_reserved_space(&start, &length);
length = 0x1000;
/* Map new address */
dprintf("ISD: %x@%x -> %x@%x, %x\n", s->ISD_length, s->ISD_start,
DPRINTF("ISD: %x@%x -> %x@%x, %x\n", s->ISD_length, s->ISD_start,
length, start, s->ISD_handle);
s->ISD_start = start;
s->ISD_length = length;
......@@ -423,7 +423,7 @@ static void gt64120_writel (void *opaque, target_phys_addr_t addr,
case GT_DEV_B3:
case GT_DEV_BOOT:
/* Not implemented */
dprintf ("Unimplemented device register offset 0x%x\n", saddr << 2);
DPRINTF ("Unimplemented device register offset 0x%x\n", saddr << 2);
break;
/* ECC */
......@@ -457,7 +457,7 @@ static void gt64120_writel (void *opaque, target_phys_addr_t addr,
case GT_DMA2_CUR:
case GT_DMA3_CUR:
/* Not implemented */
dprintf ("Unimplemented DMA register offset 0x%x\n", saddr << 2);
DPRINTF ("Unimplemented DMA register offset 0x%x\n", saddr << 2);
break;
/* DMA Channel Control */
......@@ -466,13 +466,13 @@ static void gt64120_writel (void *opaque, target_phys_addr_t addr,
case GT_DMA2_CTRL:
case GT_DMA3_CTRL:
/* Not implemented */
dprintf ("Unimplemented DMA register offset 0x%x\n", saddr << 2);
DPRINTF ("Unimplemented DMA register offset 0x%x\n", saddr << 2);
break;
/* DMA Arbiter */
case GT_DMA_ARB:
/* Not implemented */
dprintf ("Unimplemented DMA register offset 0x%x\n", saddr << 2);
DPRINTF ("Unimplemented DMA register offset 0x%x\n", saddr << 2);
break;
/* Timer/Counter */
......@@ -482,7 +482,7 @@ static void gt64120_writel (void *opaque, target_phys_addr_t addr,
case GT_TC3:
case GT_TC_CONTROL:
/* Not implemented */
dprintf ("Unimplemented timer register offset 0x%x\n", saddr << 2);
DPRINTF ("Unimplemented timer register offset 0x%x\n", saddr << 2);
break;
/* PCI Internal */
......@@ -539,19 +539,19 @@ static void gt64120_writel (void *opaque, target_phys_addr_t addr,
/* not really implemented */
s->regs[saddr] = ~(~(s->regs[saddr]) | ~(val & 0xfffffffe));
s->regs[saddr] |= !!(s->regs[saddr] & 0xfffffffe);
dprintf("INTRCAUSE %x\n", val);
DPRINTF("INTRCAUSE %x\n", val);
break;
case GT_INTRMASK:
s->regs[saddr] = val & 0x3c3ffffe;
dprintf("INTRMASK %x\n", val);
DPRINTF("INTRMASK %x\n", val);
break;
case GT_PCI0_ICMASK:
s->regs[saddr] = val & 0x03fffffe;
dprintf("ICMASK %x\n", val);
DPRINTF("ICMASK %x\n", val);
break;
case GT_PCI0_SERR0MASK:
s->regs[saddr] = val & 0x0000003f;
dprintf("SERR0MASK %x\n", val);
DPRINTF("SERR0MASK %x\n", val);
break;
/* Reserved when only PCI_0 is configured. */
......@@ -575,7 +575,7 @@ static void gt64120_writel (void *opaque, target_phys_addr_t addr,
break;
default:
dprintf ("Bad register offset 0x%x\n", (int)addr);
DPRINTF ("Bad register offset 0x%x\n", (int)addr);
break;
}
}
......@@ -815,19 +815,19 @@ static uint32_t gt64120_readl (void *opaque,
/* Interrupts */
case GT_INTRCAUSE:
val = s->regs[saddr];
dprintf("INTRCAUSE %x\n", val);
DPRINTF("INTRCAUSE %x\n", val);
break;
case GT_INTRMASK:
val = s->regs[saddr];
dprintf("INTRMASK %x\n", val);
DPRINTF("INTRMASK %x\n", val);
break;
case GT_PCI0_ICMASK:
val = s->regs[saddr];
dprintf("ICMASK %x\n", val);
DPRINTF("ICMASK %x\n", val);
break;
case GT_PCI0_SERR0MASK:
val = s->regs[saddr];
dprintf("SERR0MASK %x\n", val);
DPRINTF("SERR0MASK %x\n", val);
break;
/* Reserved when only PCI_0 is configured. */
......@@ -842,7 +842,7 @@ static uint32_t gt64120_readl (void *opaque,
default:
val = s->regs[saddr];
dprintf ("Bad register offset 0x%x\n", (int)addr);
DPRINTF ("Bad register offset 0x%x\n", (int)addr);
break;
}
......
......@@ -32,9 +32,9 @@
//#define HPET_DEBUG
#ifdef HPET_DEBUG
#define dprintf printf
#define DPRINTF printf
#else
#define dprintf(...)
#define DPRINTF(...)
#endif
static HPETState *hpet_statep;
......@@ -288,7 +288,7 @@ static uint32_t hpet_ram_readl(void *opaque, target_phys_addr_t addr)
HPETState *s = (HPETState *)opaque;
uint64_t cur_tick, index;
dprintf("qemu: Enter hpet_ram_readl at %" PRIx64 "\n", addr);
DPRINTF("qemu: Enter hpet_ram_readl at %" PRIx64 "\n", addr);
index = addr;
/*address range of all TN regs*/
if (index >= 0x100 && index <= 0x3ff) {
......@@ -311,7 +311,7 @@ static uint32_t hpet_ram_readl(void *opaque, target_phys_addr_t addr)
case HPET_TN_ROUTE:
return timer->fsb >> 32;
default:
dprintf("qemu: invalid hpet_ram_readl\n");
DPRINTF("qemu: invalid hpet_ram_readl\n");
break;
}
} else {
......@@ -323,26 +323,26 @@ static uint32_t hpet_ram_readl(void *opaque, target_phys_addr_t addr)
case HPET_CFG:
return s->config;
case HPET_CFG + 4:
dprintf("qemu: invalid HPET_CFG + 4 hpet_ram_readl \n");
DPRINTF("qemu: invalid HPET_CFG + 4 hpet_ram_readl \n");
return 0;
case HPET_COUNTER:
if (hpet_enabled())
cur_tick = hpet_get_ticks();
else
cur_tick = s->hpet_counter;
dprintf("qemu: reading counter = %" PRIx64 "\n", cur_tick);
DPRINTF("qemu: reading counter = %" PRIx64 "\n", cur_tick);
return cur_tick;
case HPET_COUNTER + 4:
if (hpet_enabled())
cur_tick = hpet_get_ticks();
else
cur_tick = s->hpet_counter;
dprintf("qemu: reading counter + 4 = %" PRIx64 "\n", cur_tick);
DPRINTF("qemu: reading counter + 4 = %" PRIx64 "\n", cur_tick);
return cur_tick >> 32;
case HPET_STATUS:
return s->isr;
default:
dprintf("qemu: invalid hpet_ram_readl\n");
DPRINTF("qemu: invalid hpet_ram_readl\n");
break;
}
}
......@@ -372,7 +372,7 @@ static void hpet_ram_writel(void *opaque, target_phys_addr_t addr,
HPETState *s = (HPETState *)opaque;
uint64_t old_val, new_val, val, index;
dprintf("qemu: Enter hpet_ram_writel at %" PRIx64 " = %#x\n", addr, value);
DPRINTF("qemu: Enter hpet_ram_writel at %" PRIx64 " = %#x\n", addr, value);
index = addr;
old_val = hpet_ram_readl(opaque, addr);
new_val = value;
......@@ -380,12 +380,12 @@ static void hpet_ram_writel(void *opaque, target_phys_addr_t addr,
/*address range of all TN regs*/
if (index >= 0x100 && index <= 0x3ff) {
uint8_t timer_id = (addr - 0x100) / 0x20;
dprintf("qemu: hpet_ram_writel timer_id = %#x \n", timer_id);
DPRINTF("qemu: hpet_ram_writel timer_id = %#x \n", timer_id);
HPETTimer *timer = &s->timer[timer_id];
switch ((addr - 0x100) % 0x20) {
case HPET_TN_CFG:
dprintf("qemu: hpet_ram_writel HPET_TN_CFG\n");
DPRINTF("qemu: hpet_ram_writel HPET_TN_CFG\n");
val = hpet_fixup_reg(new_val, old_val, HPET_TN_CFG_WRITE_MASK);
timer->config = (timer->config & 0xffffffff00000000ULL) | val;
if (new_val & HPET_TN_32BIT) {
......@@ -399,10 +399,10 @@ static void hpet_ram_writel(void *opaque, target_phys_addr_t addr,
break;
case HPET_TN_CFG + 4: // Interrupt capabilities
dprintf("qemu: invalid HPET_TN_CFG+4 write\n");
DPRINTF("qemu: invalid HPET_TN_CFG+4 write\n");
break;
case HPET_TN_CMP: // comparator register
dprintf("qemu: hpet_ram_writel HPET_TN_CMP \n");
DPRINTF("qemu: hpet_ram_writel HPET_TN_CMP \n");
if (timer->config & HPET_TN_32BIT)
new_val = (uint32_t)new_val;
if (!timer_is_periodic(timer) ||
......@@ -423,7 +423,7 @@ static void hpet_ram_writel(void *opaque, target_phys_addr_t addr,
hpet_set_timer(timer);
break;
case HPET_TN_CMP + 4: // comparator register high order
dprintf("qemu: hpet_ram_writel HPET_TN_CMP + 4\n");
DPRINTF("qemu: hpet_ram_writel HPET_TN_CMP + 4\n");
if (!timer_is_periodic(timer) ||
(timer->config & HPET_TN_SETVAL))
timer->cmp = (timer->cmp & 0xffffffffULL)
......@@ -443,10 +443,10 @@ static void hpet_ram_writel(void *opaque, target_phys_addr_t addr,
hpet_set_timer(timer);
break;
case HPET_TN_ROUTE + 4:
dprintf("qemu: hpet_ram_writel HPET_TN_ROUTE + 4\n");
DPRINTF("qemu: hpet_ram_writel HPET_TN_ROUTE + 4\n");
break;
default:
dprintf("qemu: invalid hpet_ram_writel\n");
DPRINTF("qemu: invalid hpet_ram_writel\n");
break;
}
return;
......@@ -479,7 +479,7 @@ static void hpet_ram_writel(void *opaque, target_phys_addr_t addr,
}
break;
case HPET_CFG + 4:
dprintf("qemu: invalid HPET_CFG+4 write \n");
DPRINTF("qemu: invalid HPET_CFG+4 write \n");
break;
case HPET_STATUS:
/* FIXME: need to handle level-triggered interrupts */
......@@ -489,7 +489,7 @@ static void hpet_ram_writel(void *opaque, target_phys_addr_t addr,
printf("qemu: Writing counter while HPET enabled!\n");
s->hpet_counter = (s->hpet_counter & 0xffffffff00000000ULL)
| value;
dprintf("qemu: HPET counter written. ctr = %#x -> %" PRIx64 "\n",
DPRINTF("qemu: HPET counter written. ctr = %#x -> %" PRIx64 "\n",
value, s->hpet_counter);
break;
case HPET_COUNTER + 4:
......@@ -497,11 +497,11 @@ static void hpet_ram_writel(void *opaque, target_phys_addr_t addr,
printf("qemu: Writing counter while HPET enabled!\n");
s->hpet_counter = (s->hpet_counter & 0xffffffffULL)
| (((uint64_t)value) << 32);
dprintf("qemu: HPET counter + 4 written. ctr = %#x -> %" PRIx64 "\n",
DPRINTF("qemu: HPET counter + 4 written. ctr = %#x -> %" PRIx64 "\n",
value, s->hpet_counter);
break;
default:
dprintf("qemu: invalid hpet_ram_writel\n");
DPRINTF("qemu: invalid hpet_ram_writel\n");
break;
}
}
......@@ -568,7 +568,7 @@ void hpet_init(qemu_irq *irq) {
int i, iomemtype;
HPETState *s;
dprintf ("hpet_init\n");
DPRINTF ("hpet_init\n");
s = qemu_mallocz(sizeof(HPETState));
hpet_statep = s;
......
......@@ -42,9 +42,9 @@
//#define OHCI_TIME_WARP 1
#ifdef DEBUG_OHCI
#define dprintf printf
#define DPRINTF printf
#else
#define dprintf(...)
#define DPRINTF(...)
#endif
/* Number of Downstream Ports on the root hub. */
......@@ -355,7 +355,7 @@ static void ohci_attach(USBPort *port1, USBDevice *dev)
/* send the attach message */
usb_send_msg(dev, USB_MSG_ATTACH);
dprintf("usb-ohci: Attached port %d\n", port1->index);
DPRINTF("usb-ohci: Attached port %d\n", port1->index);
} else {
/* set connect status */
if (port->ctrl & OHCI_PORT_CCS) {
......@@ -373,7 +373,7 @@ static void ohci_attach(USBPort *port1, USBDevice *dev)
usb_send_msg(dev, USB_MSG_DETACH);
}
port->port.dev = NULL;
dprintf("usb-ohci: Detached port %d\n", port1->index);
DPRINTF("usb-ohci: Detached port %d\n", port1->index);
}
if (old_state != port->ctrl)
......@@ -427,7 +427,7 @@ static void ohci_reset(void *opaque)
usb_cancel_packet(&ohci->usb_packet);
ohci->async_td = 0;
}
dprintf("usb-ohci: Reset %s\n", ohci->name);
DPRINTF("usb-ohci: Reset %s\n", ohci->name);
}
/* Get an array of dwords from main memory */
......@@ -593,7 +593,7 @@ static void ohci_async_complete_packet(USBPacket *packet, void *opaque)
{
OHCIState *ohci = opaque;
#ifdef DEBUG_PACKET
dprintf("Async packet complete\n");
DPRINTF("Async packet complete\n");
#endif
ohci->async_complete = 1;
ohci_process_lists(ohci, 1);
......@@ -648,12 +648,12 @@ static int ohci_service_iso_td(OHCIState *ohci, struct ohci_ed *ed,
#endif
if (relative_frame_number < 0) {
dprintf("usb-ohci: ISO_TD R=%d < 0\n", relative_frame_number);
DPRINTF("usb-ohci: ISO_TD R=%d < 0\n", relative_frame_number);
return 1;
} else if (relative_frame_number > frame_count) {
/* ISO TD expired - retire the TD to the Done Queue and continue with
the next ISO TD of the same ED */
dprintf("usb-ohci: ISO_TD R=%d > FC=%d\n", relative_frame_number,
DPRINTF("usb-ohci: ISO_TD R=%d > FC=%d\n", relative_frame_number,
frame_count);
OHCI_SET_BM(iso_td.flags, TD_CC, OHCI_CC_DATAOVERRUN);
ed->head &= ~OHCI_DPTR_MASK;
......@@ -856,7 +856,7 @@ static int ohci_service_td(OHCIState *ohci, struct ohci_ed *ed)
completion = (addr == ohci->async_td);
if (completion && !ohci->async_complete) {
#ifdef DEBUG_PACKET
dprintf("Skipping async TD\n");
DPRINTF("Skipping async TD\n");
#endif
return 1;
}
......@@ -907,14 +907,14 @@ static int ohci_service_td(OHCIState *ohci, struct ohci_ed *ed)
flag_r = (td.flags & OHCI_TD_R) != 0;
#ifdef DEBUG_PACKET
dprintf(" TD @ 0x%.8x %" PRId64 " bytes %s r=%d cbp=0x%.8x be=0x%.8x\n",
DPRINTF(" TD @ 0x%.8x %" PRId64 " bytes %s r=%d cbp=0x%.8x be=0x%.8x\n",
addr, len, str, flag_r, td.cbp, td.be);
if (len > 0 && dir != OHCI_TD_DIR_IN) {
dprintf(" data:");
DPRINTF(" data:");
for (i = 0; i < len; i++)
printf(" %.2x", ohci->usb_buf[i]);
dprintf("\n");
DPRINTF("\n");
}
#endif
if (completion) {
......@@ -935,7 +935,7 @@ static int ohci_service_td(OHCIState *ohci, struct ohci_ed *ed)
timely manner.
*/
#ifdef DEBUG_PACKET
dprintf("Too many pending packets\n");
DPRINTF("Too many pending packets\n");
#endif
return 1;
}
......@@ -951,7 +951,7 @@ static int ohci_service_td(OHCIState *ohci, struct ohci_ed *ed)
break;
}
#ifdef DEBUG_PACKET
dprintf("ret=%d\n", ret);
DPRINTF("ret=%d\n", ret);
#endif
if (ret == USB_RET_ASYNC) {
ohci->async_td = addr;
......@@ -962,10 +962,10 @@ static int ohci_service_td(OHCIState *ohci, struct ohci_ed *ed)
if (dir == OHCI_TD_DIR_IN) {
ohci_copy_td(ohci, &td, ohci->usb_buf, ret, 1);
#ifdef DEBUG_PACKET
dprintf(" data:");
DPRINTF(" data:");
for (i = 0; i < ret; i++)
printf(" %.2x", ohci->usb_buf[i]);
dprintf("\n");
DPRINTF("\n");
#endif
} else {
ret = len;
......@@ -994,21 +994,21 @@ static int ohci_service_td(OHCIState *ohci, struct ohci_ed *ed)
ed->head |= OHCI_ED_C;
} else {
if (ret >= 0) {
dprintf("usb-ohci: Underrun\n");
DPRINTF("usb-ohci: Underrun\n");
OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_DATAUNDERRUN);
} else {
switch (ret) {
case USB_RET_NODEV:
OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_DEVICENOTRESPONDING);
case USB_RET_NAK:
dprintf("usb-ohci: got NAK\n");
DPRINTF("usb-ohci: got NAK\n");
return 1;
case USB_RET_STALL:
dprintf("usb-ohci: got STALL\n");
DPRINTF("usb-ohci: got STALL\n");
OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_STALL);
break;
case USB_RET_BABBLE:
dprintf("usb-ohci: got BABBLE\n");
DPRINTF("usb-ohci: got BABBLE\n");
OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_DATAOVERRUN);
break;
default:
......@@ -1067,7 +1067,7 @@ static int ohci_service_ed_list(OHCIState *ohci, uint32_t head, int completion)
while ((ed.head & OHCI_DPTR_MASK) != ed.tail) {
#ifdef DEBUG_PACKET
dprintf("ED @ 0x%.8x fa=%u en=%u d=%u s=%u k=%u f=%u mps=%u "
DPRINTF("ED @ 0x%.8x fa=%u en=%u d=%u s=%u k=%u f=%u mps=%u "
"h=%u c=%u\n head=0x%.8x tailp=0x%.8x next=0x%.8x\n", cur,
OHCI_BM(ed.flags, ED_FA), OHCI_BM(ed.flags, ED_EN),
OHCI_BM(ed.flags, ED_D), (ed.flags & OHCI_ED_S)!= 0,
......@@ -1107,7 +1107,7 @@ static void ohci_process_lists(OHCIState *ohci, int completion)
{
if ((ohci->ctl & OHCI_CTL_CLE) && (ohci->status & OHCI_STATUS_CLF)) {
if (ohci->ctrl_cur && ohci->ctrl_cur != ohci->ctrl_head)
dprintf("usb-ohci: head %x, cur %x\n",
DPRINTF("usb-ohci: head %x, cur %x\n",
ohci->ctrl_head, ohci->ctrl_cur);
if (!ohci_service_ed_list(ohci, ohci->ctrl_head, completion)) {
ohci->ctrl_cur = 0;
......@@ -1191,7 +1191,7 @@ static int ohci_bus_start(OHCIState *ohci)
return 0;
}
dprintf("usb-ohci: %s: USB Operational\n", ohci->name);
DPRINTF("usb-ohci: %s: USB Operational\n", ohci->name);
ohci_sof(ohci);
......@@ -1244,7 +1244,7 @@ static void ohci_set_frame_interval(OHCIState *ohci, uint16_t val)
val &= OHCI_FMI_FI;
if (val != ohci->fi) {
dprintf("usb-ohci: %s: FrameInterval = 0x%x (%u)\n",
DPRINTF("usb-ohci: %s: FrameInterval = 0x%x (%u)\n",
ohci->name, ohci->fi, ohci->fi);
}
......@@ -1283,14 +1283,14 @@ static void ohci_set_ctl(OHCIState *ohci, uint32_t val)
break;
case OHCI_USB_SUSPEND:
ohci_bus_stop(ohci);
dprintf("usb-ohci: %s: USB Suspended\n", ohci->name);
DPRINTF("usb-ohci: %s: USB Suspended\n", ohci->name);
break;
case OHCI_USB_RESUME:
dprintf("usb-ohci: %s: USB Resume\n", ohci->name);
DPRINTF("usb-ohci: %s: USB Resume\n", ohci->name);
break;
case OHCI_USB_RESET:
ohci_reset(ohci);
dprintf("usb-ohci: %s: USB Reset\n", ohci->name);
DPRINTF("usb-ohci: %s: USB Reset\n", ohci->name);
break;
}
}
......@@ -1335,7 +1335,7 @@ static void ohci_set_hub_status(OHCIState *ohci, uint32_t val)
for (i = 0; i < ohci->num_ports; i++)
ohci_port_power(ohci, i, 0);
dprintf("usb-ohci: powered down all ports\n");
DPRINTF("usb-ohci: powered down all ports\n");
}
if (val & OHCI_RHS_LPSC) {
......@@ -1343,7 +1343,7 @@ static void ohci_set_hub_status(OHCIState *ohci, uint32_t val)
for (i = 0; i < ohci->num_ports; i++)
ohci_port_power(ohci, i, 1);
dprintf("usb-ohci: powered up all ports\n");
DPRINTF("usb-ohci: powered up all ports\n");
}
if (val & OHCI_RHS_DRWE)
......@@ -1375,10 +1375,10 @@ static void ohci_port_set_status(OHCIState *ohci, int portnum, uint32_t val)
ohci_port_set_if_connected(ohci, portnum, val & OHCI_PORT_PES);
if (ohci_port_set_if_connected(ohci, portnum, val & OHCI_PORT_PSS))
dprintf("usb-ohci: port %d: SUSPEND\n", portnum);
DPRINTF("usb-ohci: port %d: SUSPEND\n", portnum);
if (ohci_port_set_if_connected(ohci, portnum, val & OHCI_PORT_PRS)) {
dprintf("usb-ohci: port %d: RESET\n", portnum);
DPRINTF("usb-ohci: port %d: RESET\n", portnum);
usb_send_msg(port->port.dev, USB_MSG_RESET);
port->ctrl &= ~OHCI_PORT_PRS;
/* ??? Should this also set OHCI_PORT_PESC. */
......@@ -1680,7 +1680,7 @@ static void usb_ohci_init(OHCIState *ohci, DeviceState *dev,
usb_bit_time = 1;
}
#endif
dprintf("usb-ohci: usb_bit_time=%" PRId64 " usb_frame_time=%" PRId64 "\n",
DPRINTF("usb-ohci: usb_bit_time=%" PRId64 " usb_frame_time=%" PRId64 "\n",
usb_frame_time, usb_bit_time);
}
......
......@@ -71,7 +71,7 @@
#define NB_PORTS 2
#ifdef DEBUG
#define dprintf printf
#define DPRINTF printf
static const char *pid2str(int pid)
{
......@@ -84,7 +84,7 @@ static const char *pid2str(int pid)
}